Custom IC design and physical verification (DRC/LVS) of a 2:1 CMOS Multiplexer using Cadence Virtuoso in 45nm GPDK.
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Jul 23, 2026
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drc-lvs
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Notes on analog and memory IC layout. Covers symmetry, matching, parasitics, and verification practices for reproducible design.
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Mar 20, 2026
Full-custom 6T SRAM bitcell and 8×8 array in 180 nm CMOS from a parameterised SKILL generator; array signed off DRC-clean and LVS-matched against the full foundry deck.
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Sep 6, 2026 - Common Lisp
Designed and simulated ultra low-voltage, low-power CMOS 5:2 compressors in Cadence Virtuoso, based on Figure 13 from the referenced IEEE paper. Focused on optimizing power, delay, and area for efficient high-speed arithmetic circuits used in VLSI and DSP applications.
dsp digital-logic vlsi cadence-virtuoso cadence transient-analysis cmos low-power microelectronics ic-design vlsi-design arithmetic-circuits 45nm layout-design power-delay-product drc-lvs transistor-sizing gpdk045 compressor-circuit ultra-low-voltage
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Mar 22, 2026
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