Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.
verilog-hdl fixed-point-arithmetic cadence-innovus pipeline-design fsm-design cadence-genus tsmc-180nm dnn-hardware-accelerators
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Updated
Apr 2, 2026