This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.
Design Rule Check engine for auto-generated diagrams — crossing minimization, spacing, label overlap detection and auto-fix
Citation-grounded RAG assistant for semiconductor PDK/EDA engineers. Answers design-rule questions and drafts DRC/LVS snippet pseudocode, grounded in public PDK docs with a built-in citation guard.
Design rule checker for VLSI layouts
Design-rule check: a GDS layout + a rule deck in, geometry violations out.
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