Hardware Abstraction Layer for ATSAME54 microcontrollers
-
Updated
Nov 14, 2022 - C
Hardware Abstraction Layer for ATSAME54 microcontrollers
10BASE-T1S hands-on lab: ATSAME54 + LAN867x Harmony 3 firmware with an OLED1 display, including the lab manual and reference datasheets.
10BASE-T1S/PLCA autoconfiguration on ATSAME54 + LAN865x/LAN867x (Harmony 3): FreeRTOS heap rework, packet magic number, Wireshark Lua dissector and a multi-board flasher.
10BASE-T1S multi-node demo on ATSAME54 + LAN865x/LAN867x (Harmony 3) with four builds for four PLCA node IDs.
ADC sampling with DMA double buffering on the ATSAME54 (SAM E54 Xplained Pro, Harmony 3).
PTP (IEEE 1588-2008) hardware timestamping over 10BASE-T1S on ATSAME54P20A + LAN8651 (Harmony 3), with a Python test harness, adaptive drift filter and cross-board sync measurements.
T1S Network to 100BaseT Bridge
To associate your repository with the atsame54 topic, visit your repo's landing page and select "manage topics."