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9 changes: 9 additions & 0 deletions .gitattributes
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# Set all the text files to use LF line endings.
* text=auto eol=lf

# Set all the binary files to use binary mode(avoid corruption).
*.png binary
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*.tar.gz binary
544 changes: 272 additions & 272 deletions cgra/CgraRTL.py

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764 changes: 382 additions & 382 deletions cgra/CgraTemplateRTL.py

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526 changes: 263 additions & 263 deletions cgra/CgraWithContextSwitchRTL.py

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544 changes: 272 additions & 272 deletions cgra/CgraWithStreamingLoadRTL.py

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780 changes: 390 additions & 390 deletions controller/ControllerRTL.py

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138 changes: 69 additions & 69 deletions mem/ctrl/RingMultiCtrlMemDynamicRTL.py
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"""
==========================================================================
RingMultiCtrlMemDynamicRTL.py
==========================================================================
Ring connecting multiple control memories.
Author : Cheng Tan
Date : Dec 22, 2024
"""
from pymtl3 import *
from pymtl3.stdlib.primitive import RegisterFile
from .CtrlMemDynamicRTL import CtrlMemDynamicRTL
from ...lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL as RecvIfcRTL
from ...lib.basic.val_rdy.ifcs import ValRdySendIfcRTL as SendIfcRTL
from ...lib.opt_type import *
from ...noc.PyOCN.pymtl3_net.ocnlib.ifcs.positions import mk_ring_pos
from ...noc.PyOCN.pymtl3_net.ringnet.RingNetworkRTL import RingNetworkRTL
from ...lib.util.data_struct_attr import *
class RingMultiCtrlMemDynamicRTL(Component):
def construct(s, CtrlPktType, CgraPayloadType,
width, height, ctrl_mem_size, num_fu_inports,
num_fu_outports, num_tile_inports, num_tile_outports,
ctrl_count_per_iter = 4, total_ctrl_steps = 4):
CtrlSignalType = CgraPayloadType.get_field_type(kAttrCtrl)
# Constant
num_tiles = width * height
s.num_tiles = width * height
CtrlRingPos = mk_ring_pos(num_tiles + 1)
# Interface
s.send_ctrl = [SendIfcRTL(CtrlSignalType) for _ in range(s.num_tiles)]
s.recv_pkt_from_controller = RecvIfcRTL(CtrlPktType)
s.send_to_controller_pkt = SendIfcRTL(CtrlPktType)
# Components
s.ctrl_memories = [
CtrlMemDynamicRTL(CtrlPktType,
ctrl_mem_size, num_fu_inports,
num_fu_outports, num_tile_inports,
num_tile_outports, 1, num_tiles, ctrl_count_per_iter,
total_ctrl_steps) for terminal_id in range(s.num_tiles)]
s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, num_tiles + 1, 1)
# Connections
for i in range(s.num_tiles):
s.ctrl_memories[i].cgra_id //= 0
s.ctrl_memories[i].tile_id //= i
s.ctrl_memories[i].recv_from_element.val //= 1
s.ctrl_memories[i].recv_from_element.msg //= CgraPayloadType()
for i in range(s.num_tiles):
s.ctrl_ring.send[i] //= s.ctrl_memories[i].recv_pkt_from_controller
s.ctrl_ring.send[s.num_tiles] //= s.send_to_controller_pkt
for i in range(s.num_tiles):
s.ctrl_ring.recv[i] //= s.ctrl_memories[i].send_pkt_to_controller
s.ctrl_ring.recv[s.num_tiles] //= s.recv_pkt_from_controller
for i in range(s.num_tiles):
s.ctrl_memories[i].send_ctrl //= s.send_ctrl[i]
def line_trace(s):
res = "||\n".join([(("[ctrl_memory["+str(i)+"]: ") + x.line_trace())
for (i,x) in enumerate(s.ctrl_memories)])
res += " ## ctrl_ring: " + s.ctrl_ring.line_trace()
return res
"""
==========================================================================
RingMultiCtrlMemDynamicRTL.py
==========================================================================
Ring connecting multiple control memories.

Author : Cheng Tan
Date : Dec 22, 2024
"""

from pymtl3 import *
from pymtl3.stdlib.primitive import RegisterFile
from .CtrlMemDynamicRTL import CtrlMemDynamicRTL
from ...lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL as RecvIfcRTL
from ...lib.basic.val_rdy.ifcs import ValRdySendIfcRTL as SendIfcRTL
from ...lib.opt_type import *
from ...noc.PyOCN.pymtl3_net.ocnlib.ifcs.positions import mk_ring_pos
from ...noc.PyOCN.pymtl3_net.ringnet.RingNetworkRTL import RingNetworkRTL
from ...lib.util.data_struct_attr import *

class RingMultiCtrlMemDynamicRTL(Component):
def construct(s, CtrlPktType, CgraPayloadType,
width, height, ctrl_mem_size, num_fu_inports,
num_fu_outports, num_tile_inports, num_tile_outports,
ctrl_count_per_iter = 4, total_ctrl_steps = 4):
CtrlSignalType = CgraPayloadType.get_field_type(kAttrCtrl)
# Constant
num_tiles = width * height
s.num_tiles = width * height
CtrlRingPos = mk_ring_pos(num_tiles + 1)

# Interface
s.send_ctrl = [SendIfcRTL(CtrlSignalType) for _ in range(s.num_tiles)]
s.recv_pkt_from_controller = RecvIfcRTL(CtrlPktType)
s.send_to_controller_pkt = SendIfcRTL(CtrlPktType)

# Components
s.ctrl_memories = [
CtrlMemDynamicRTL(CtrlPktType,
ctrl_mem_size, num_fu_inports,
num_fu_outports, num_tile_inports,
num_tile_outports, 1, num_tiles, ctrl_count_per_iter,
total_ctrl_steps) for terminal_id in range(s.num_tiles)]
s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, num_tiles + 1, 1)

# Connections
for i in range(s.num_tiles):
s.ctrl_memories[i].cgra_id //= 0
s.ctrl_memories[i].tile_id //= i
s.ctrl_memories[i].recv_from_element.val //= 1
s.ctrl_memories[i].recv_from_element.msg //= CgraPayloadType()

for i in range(s.num_tiles):
s.ctrl_ring.send[i] //= s.ctrl_memories[i].recv_pkt_from_controller
s.ctrl_ring.send[s.num_tiles] //= s.send_to_controller_pkt

for i in range(s.num_tiles):
s.ctrl_ring.recv[i] //= s.ctrl_memories[i].send_pkt_to_controller
s.ctrl_ring.recv[s.num_tiles] //= s.recv_pkt_from_controller

for i in range(s.num_tiles):
s.ctrl_memories[i].send_ctrl //= s.send_ctrl[i]

def line_trace(s):
res = "||\n".join([(("[ctrl_memory["+str(i)+"]: ") + x.line_trace())
for (i,x) in enumerate(s.ctrl_memories)])
res += " ## ctrl_ring: " + s.ctrl_ring.line_trace()
return res

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