M8: MIR and below

[tamnd]

Seven weeks. Part VII, from MIR down to the MC layer. Ten lessons, five blueprints, and the register allocation material that most people never get a clear picture of.

Exit criterion. M06's boss fight, predict the allocation and then force a spill and explain it, is completed by testers who had never read a MIR dump before Part VII.

Tasks

• M01 to M10
• BP-CG-MIR, BP-CG-REGALLOC, BP-CG-FRAME, BP-CG-CC, BP-CG-MC
• irx.mir and irx.mca
• The MIRWalker, IntervalChart and MCATimeline widgets
• The register allocation animations

Gates

• M06's boss fight is completed by testers with no prior MIR experience
• llvm-exegesis availability at E0 is settled one way or the other and the affected lessons say what they say

llvm-exegesis needs performance counters, which a Colab VM may or may not expose. Settle it, do not leave it as a maybe, and if the answer is no then the lessons that wanted it say so plainly and use a recording instead of pretending.