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feat: integrate Tier 6 distributed monad into build and add tests #508

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6627908
feat: integrate Tier 6 distributed monad into build and add tests
google-labs-jules[bot] Mar 30, 2026
7e7f82a
fix: correct determinism claims link and missing glossary ref
google-labs-jules[bot] Mar 30, 2026
832b7b0
fix: MSVC build failures in ternaryos HAL tests and GICv3 driver
google-labs-jules[bot] Mar 30, 2026
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5 changes: 5 additions & 0 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -210,6 +210,7 @@ add_library(t81_experimental STATIC
experimental/tiers/cog/tier4/tier4_loop.cpp
experimental/distributed/distributed.cpp
experimental/tiers/cog/tier5/infinite.cpp
experimental/tiers/cog/tier6/distributed_monad.cpp
)
target_link_libraries(t81_experimental PUBLIC t81_core)
target_compile_features(t81_experimental PUBLIC ${T81_CXX_STD_FEATURE})
Expand Down Expand Up @@ -2380,6 +2381,9 @@ add_test(NAME t81lang_surface_gate_test COMMAND t81lang_surface_gate_test)
target_link_libraries(t81_ethics_test PRIVATE t81_core t81_axion)
add_test(NAME t81_ethics_test COMMAND t81_ethics_test)

add_executable(t81_tier6_test tests/cpp/tier6_test.cpp)
target_link_libraries(t81_tier6_test PRIVATE t81_core t81_experimental t81_tracing)
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@greptile-apps greptile-apps bot Mar 30, 2026

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P2 Redundant t81_tracing link dependency

t81_tracing is declared as an OBJECT library (line 195) and its objects are already compiled directly into t81_core via target_sources(t81_core PRIVATE $<TARGET_OBJECTS:t81_tracing>) (line 202). Listing it again here is redundant — the symbols are already present through t81_core. Compare with the analogous t81_tier5_test target which links only t81_core t81_experimental.

Suggested change
target_link_libraries(t81_tier6_test PRIVATE t81_core t81_experimental t81_tracing)
target_link_libraries(t81_tier6_test PRIVATE t81_core t81_experimental)


add_executable(t81_ethics_invariants_test tests/cpp/test_ethics_invariants.cpp)
target_link_libraries(t81_ethics_invariants_test PRIVATE t81_core t81_axion)
add_test(NAME t81_ethics_invariants_test COMMAND t81_ethics_invariants_test)
Expand Down Expand Up @@ -3301,6 +3305,7 @@ target_link_libraries(axion_policy_segment_event_test PRIVATE t81_isa t81_vm)
canonfs_axion_trace_test
t81_tier4_test
t81_tier5_test
t81_tier6_test
t81_infinite_opcodes_test
t81_tier4_vm_test
t81_tier4_distributed_test
Expand Down
4 changes: 2 additions & 2 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,7 @@ deny infer reason "unapproved-model";

As of March 2026, The T81 deterministic core (ISA, VM, data types) is stable and governed by a monthly C2 review cadence. Active risks, implementation matrix, and decision logs are tracked in [`docs/status/`](docs/status/).

- **Determinism claims** are bounded by the [Deterministic Core Profile](docs/status/SYSTEM_STATUS.md) and verified via CI gates.
- **Determinism claims** are bounded by the [Determinism Surface Registry](docs/governance/DETERMINISM_SURFACE_REGISTRY.md) and verified via CI gates.
- See the full [Project Roadmap & Governance Status](docs/status/ROADMAP.md) and [Getting Started & Installation](docs/user-guide/quickstart/INSTALL.md) for details.

## What T81 is Not (Yet)
Expand All @@ -167,7 +167,7 @@ T81 prioritizes **verifiability, determinism, and governance** over broad compat

## Architecture Overview

For deeper technical mapping (Natural Language Space → Code Entity Space), see the [Project Overview](docs/index.md) and [Glossary](docs/glossary.md) in the DeepWiki.
For deeper technical mapping (Natural Language Space → Code Entity Space), see the [Project Overview](docs/index.md) in the DeepWiki.

## Long-term direction

Expand Down
59 changes: 26 additions & 33 deletions ternaryos/dev/gicv3.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11,20 +11,18 @@ namespace t81::ternaryos::dev {

// ── Hardware access helpers ──────────────────────────────────────────────────

#if defined(__aarch64__) && !defined(__APPLE__) && \
!defined(T81_TERNARYOS_HOSTED_BUILD) && !defined(_MSC_VER)
#if defined(__aarch64__) && !defined(__APPLE__) && !defined(T81_TERNARYOS_HOSTED_BUILD) && \
!defined(_MSC_VER)

static inline void gicd_write32(uint64_t base, uint64_t off,
uint32_t val) noexcept {
static inline void gicd_write32(uint64_t base, uint64_t off, uint32_t val) noexcept {
*reinterpret_cast<volatile uint32_t*>(base + off) = val;
}

static inline uint32_t gicd_read32(uint64_t base, uint64_t off) noexcept {
return *reinterpret_cast<const volatile uint32_t*>(base + off);
}

static inline void gicd_write64(uint64_t base, uint64_t off,
uint64_t val) noexcept {
static inline void gicd_write64(uint64_t base, uint64_t off, uint64_t val) noexcept {
*reinterpret_cast<volatile uint64_t*>(base + off) = val;
}

Expand All @@ -39,20 +37,20 @@ static inline void gicd_wait_rwp(uint64_t dist_base) noexcept {

static inline void icc_sre_el1_write(uint64_t val) noexcept {
__asm__ volatile("msr icc_sre_el1, %0\n\t"
"isb"
:: "r"(val) : "memory");
"isb" ::"r"(val)
: "memory");
}

static inline void icc_pmr_el1_write(uint64_t val) noexcept {
__asm__ volatile("msr icc_pmr_el1, %0\n\t"
"isb"
:: "r"(val) : "memory");
"isb" ::"r"(val)
: "memory");
}

static inline void icc_igrpen1_el1_write(uint64_t val) noexcept {
__asm__ volatile("msr icc_igrpen1_el1, %0\n\t"
"isb"
:: "r"(val) : "memory");
"isb" ::"r"(val)
: "memory");
}

static inline uint64_t icc_iar1_el1_read() noexcept {
Expand All @@ -62,7 +60,7 @@ static inline uint64_t icc_iar1_el1_read() noexcept {
}

static inline void icc_eoir1_el1_write(uint64_t val) noexcept {
__asm__ volatile("msr icc_eoir1_el1, %0" :: "r"(val) : "memory");
__asm__ volatile("msr icc_eoir1_el1, %0" ::"r"(val) : "memory");
}

#else // hosted build — all hardware access is a no-op
Expand All @@ -75,9 +73,7 @@ static inline void gicd_wait_rwp(uint64_t) noexcept {}
static inline void icc_sre_el1_write(uint64_t) noexcept {}
static inline void icc_pmr_el1_write(uint64_t) noexcept {}
static inline void icc_igrpen1_el1_write(uint64_t) noexcept {}
static inline uint64_t icc_iar1_el1_read() noexcept {
return kGicSpuriousIntid;
}
static inline uint64_t icc_iar1_el1_read() noexcept { return kGicSpuriousIntid; }
static inline void icc_eoir1_el1_write(uint64_t) noexcept {}

#endif
Expand All @@ -87,27 +83,25 @@ static inline void icc_eoir1_el1_write(uint64_t) noexcept {}
/// GICD_IGROUPR[n]: each register covers 32 consecutive INTIDs.
static void set_intid_group1(uint64_t dist_base, uint32_t intid) noexcept {
const uint32_t reg_idx = intid / 32u;
const uint32_t bit = 1u << (intid % 32u);
const uint64_t off = kGicdIgrouprN + reg_idx * 4u;
const uint32_t cur = gicd_read32(dist_base, off);
const uint32_t bit = 1u << (intid % 32u);
const uint64_t off = kGicdIgrouprN + reg_idx * 4u;
const uint32_t cur = gicd_read32(dist_base, off);
gicd_write32(dist_base, off, cur | bit);
}

/// GICD_ISENABLER[n] / GICD_ICENABLER[n].
static void set_intid_enable(uint64_t dist_base, uint32_t intid,
bool enable) noexcept {
static void set_intid_enable(uint64_t dist_base, uint32_t intid, bool enable) noexcept {
const uint32_t reg_idx = intid / 32u;
const uint32_t bit = 1u << (intid % 32u);
const uint32_t bit = 1u << (intid % 32u);
const uint64_t base_off = enable ? kGicdIsenabler0 : kGicdIcenabler0;
gicd_write32(dist_base, base_off + reg_idx * 4u, bit);
}

/// GICD_IPRIORITYR[n]: one byte per INTID, packed 4-per-word.
static void set_intid_priority(uint64_t dist_base, uint32_t intid,
uint8_t priority) noexcept {
const uint32_t reg_idx = intid / 4u;
static void set_intid_priority(uint64_t dist_base, uint32_t intid, uint8_t priority) noexcept {
const uint32_t reg_idx = intid / 4u;
const uint32_t byte_off = intid % 4u;
const uint64_t off = kGicdIpriorityrN + reg_idx * 4u;
const uint64_t off = kGicdIpriorityrN + reg_idx * 4u;
uint32_t cur = gicd_read32(dist_base, off);
cur &= ~(0xFFu << (byte_off * 8u));
cur |= (static_cast<uint32_t>(priority) << (byte_off * 8u));
Expand All @@ -133,7 +127,10 @@ void gicv3_init(uint64_t dist_base, uint64_t redist_base) noexcept {
if (!(gicd_read32(redist_base, kGicrWaker) & kGicrWakerChildrenAsleep)) {
break;
}
#if defined(__aarch64__) && !defined(__APPLE__) && !defined(T81_TERNARYOS_HOSTED_BUILD) && \
!defined(_MSC_VER)
__asm__ volatile("isb");
#endif
}

// 3. Set all SGIs (0..15) and PPIs (16..31) in the SGI frame to Group 1 NS.
Expand Down Expand Up @@ -164,14 +161,12 @@ void gicv3_disable_spi(uint64_t dist_base, uint32_t intid) noexcept {
set_intid_enable(dist_base, intid, false);
}

void gicv3_set_priority(uint64_t dist_base, uint32_t intid,
uint8_t priority) noexcept {
void gicv3_set_priority(uint64_t dist_base, uint32_t intid, uint8_t priority) noexcept {
if (intid > kGicMaxIntid) return;
set_intid_priority(dist_base, intid, priority);
}

void gicv3_route_spi(uint64_t dist_base, uint32_t intid,
uint8_t aff0) noexcept {
void gicv3_route_spi(uint64_t dist_base, uint32_t intid, uint8_t aff0) noexcept {
if (intid < 32u || intid > kGicMaxIntid) return;
// GICD_IROUTER: 64-bit, Aff0 in bits [7:0], IRM=0 (route to specific CPU).
const uint64_t off = kGicdIrouterN + (intid - 32u) * 8u;
Expand All @@ -182,9 +177,7 @@ uint32_t gicv3_acknowledge() noexcept {
return static_cast<uint32_t>(icc_iar1_el1_read() & 0xFFFFFFu);
}

void gicv3_eoi(uint32_t intid) noexcept {
icc_eoir1_el1_write(static_cast<uint64_t>(intid));
}
void gicv3_eoi(uint32_t intid) noexcept { icc_eoir1_el1_write(static_cast<uint64_t>(intid)); }

void gicv3_enable_ppi(uint64_t redist_base, uint32_t intid) noexcept {
if (intid < 16u || intid > 31u) return;
Expand Down
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