Skip to content

fix: refactor image load and add i/dcache flush ops#79

Merged
liulog merged 9 commits intosyswonder:mainfrom
liulog:main
Mar 18, 2026
Merged

fix: refactor image load and add i/dcache flush ops#79
liulog merged 9 commits intosyswonder:mainfrom
liulog:main

Conversation

@liulog
Copy link
Contributor

@liulog liulog commented Mar 3, 2026

For situations requiring a virtual machine restart: Due to residual guest data in memory/cache, guest instances that are not starting for the first time may be affected by this residual data.

When the system is running, it is necessary to clear the memory allocated to the virtual machine. At the same time, before startup, the kernel image and device tree need to be flushed to memory to avoid errors caused by fetching instructions directly from memory without caching in the early stages of virtual machine startup.

In addition, the cpu cores allocated to virtual machines should ideally perform TLB and cache cleanup operations locally to prevent the virtual machine from being affected by dirty data after the MMU is enabled or the cache is enabled. This should be done by the Hypervisor(hvisor), so changes to this part will be described in a subsequent hvisor PR.

@liulog
Copy link
Contributor Author

liulog commented Mar 3, 2026

Add one json filed, setting need_clear to true will execute clearing operations.

For example:

image

@liulog
Copy link
Contributor Author

liulog commented Mar 3, 2026

Testing revealed that performing a flush operation after memset 0 or binding hvisor-tool to a specific CPU core both achieve the desired result.

This means either binding to a CPU core or clearing followed by a flush. The ultimate goal is to ensure that the data in memory is clean and undisturbed.

The flush operation is used here to ensure that the clear 0 operation is also written in memory, so that any CPU executing the load image will see a clean memory space.

@caodg caodg requested review from ZhongkaiXu and agicy March 8, 2026 13:22
@liulog liulog closed this Mar 11, 2026
@liulog liulog reopened this Mar 14, 2026
@liulog liulog changed the title fix: add ram clear & flush cache fix: refactor image load and add i/dcache flush ops Mar 14, 2026
@agicy
Copy link
Contributor

agicy commented Mar 17, 2026

Could you please sync your branch with the target (base) branch? This will help eliminate the unrelated eventfd changes in the diff and make the review much cleaner.

@liulog liulog requested a review from agicy March 17, 2026 13:16
@ZhongkaiXu
Copy link
Contributor

Approved.

@liulog liulog merged commit b9f9b8f into syswonder:main Mar 18, 2026
1 check passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants