VLSI engineer with interests in RTL design, digital verification, and system-level understanding.
Currently pursuing a PG Diploma in VLSI Design at C-DAC Pune, focusing on frontend design and verification workflows.
I work primarily in digital design and verification, with a design-oriented mindset that helps me understand failure modes and corner cases early.
My background includes exposure to analog fundamentals and backend concepts, which helps me reason about timing, constraints, and implementation trade-offs.
I am currently strengthening my skills in SystemVerilog and UVM-based verification, along with Linux and TCL-based automation, through hands-on coursework and projects at C-DAC.
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PG Diploma in VLSI Design — C-DAC Pune (ongoing)
- Frontend RTL design
- SystemVerilog & UVM verification
- System architecture concepts
- Linux, TCL scripting, and automation
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Master of Science (Electronics & Communication Engineering) — UIET Kanpur
- HDL & Programming: Verilog, SystemVerilog, C/C++, Python
- Verification: UVM, constrained-random testing, functional coverage
- Modeling & Reference: MATLAB-based golden models
- EDA Tools: Vivado, OpenROAD/OpenLane, Cadence tools, LTSpice, Virtuoso
- Scripting & Environment: Linux, TCL, Makefiles, Bash, Latex
- Operating Systems: Linux (Ubuntu, RedHat), Windows
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RTL-to-GDSII Implementation of 100-Tap Digital FIR Filter
RTL design, MATLAB golden reference modelling, and physical implementation using the OpenROAD flow with timing considerations. -
C-DAC Academic Project (Ongoing)
Small-scale digital design with both ideal and timing-aware models, verified using a UVM-based environment under a constrained timeline.
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VLSI Design Intern — IIIT Allahabad (Jun 2023 – Jul 2023)
Worked with Cadence, Synopsys tools, and Xilinx Vivado on digital design-related tasks. -
IT Administrator — Omega Career Institute (Jun 2017 – Aug 2020)
Automated internal systems and assisted with platform migration to Google Cloud.
- RF-CMOS Integrated Circuits — IIIT Allahabad
- Quantum Communication & Machine Learning — IIT BHU
- Robust VLSI Circuit Design — IIT Roorkee
- Secure Computing Techniques — ISSS
Last updated: January 15, 2026