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HFMA2.MMA translates as HFMA2, and .RELU keeps a NaN result (chain change) - #2049
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…re_orin.py runs about 190 operations, each the GPU compiler's own machine code for one PTX operation, through the translator, spirv-cross, the chain's MSL rewrites and Metal on this Mac's GPU, and compares every output word with what a Jetson Orin (sm_87) computed from the same 1,024 input rows. The translator tests checked the MSL a few encodings give, not the values; this one finds the FSETP.NE, SHFL lane, F2FP, rounding-mode and signed-zero differences the tracking issue lists, which KNOWN names until each fix takes its entry out. dm/gfx/tools/ampere_orin/capture.py records the fixture on any Linux machine with an Ampere GPU and NVIDIA's driver, with no toolkit or compiler on either side
…ompiler emits it for fma.rn.f16x2 and, far more often, to load a 32-bit constant (HFMA2.MMA Rd, -RZ, RZ, 0, imm) in integer division, 64-bit integer arithmetic, mul24, F2I to 64 bits and TF32 conversion, and the translator refused opcodes 0x235 and 0x435. It encodes like HFMA2 apart from opcode bit 2, so 0x035 now goes to HFMA2's emitter in every form and gives the same MSL. HFMA2 / HMUL2 .RELU also keeps a NaN result a NaN, as PTX's .relu does, instead of clamping it to 0. test_dmsh_ampere_orin.py: of the 17 ops that failed to translate, hfma2, hfma2_sat, hfma2_relu (314 of 2,048 lanes with the old .RELU), f2f_tf32, idiv_u32, idiv_u32_by_7, irem_s32, iadd64, isub64, imul64 and imul24 now match in every lane beyond NaN bits; mufu_rcp differs by 1 ULP from Metal's reciprocal as mufu_rcp_ftz does and moves to APPROX; hfma2_ftz differs where f16 denormals are not flushed, and fdiv_rn, f2i_s64, dadd and dmul now stop at FCHK, F2I.S64, DADD and DMUL; chain ffb778cb19be
This was referenced Nov 9, 2026
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…s#2049), with this branch's translator rebuilt from its own source; with seedds#2048's .FTZ fix here, hfma2_ftz matches the Orin; chain 178829b4ca05
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…MMA here, f2i_s64 matches the Orin (PR seedds#2059), with this branch's translator rebuilt from its own source; chain 6a270099b402
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Part of the Ampere accuracy series (#2040). It depends on #2041 for the test: the commits before this PR's own are #2041's and drop out once it lands, so this PR's own change is the last commit.
What and why
HFMA2.MMA is HFMA2 issued on the tensor pipe. ptxas emits it for ordinary
fma.rn.f16x2, and even more often as a way to load a 32-bit constant:HFMA2.MMA Rd, -RZ, RZ, 0, imm. The translator refused it (opcodes 0x235 and 0x435), so any shader with one failed to translate. None of Ocarina of Time's translated shaders has one, but the compiler emits it for plain PTX, so other games' shaders can.Its fields are HFMA2's; only opcode bit 2 differs (0x035 against 0x031 in the low 9 bits). That holds in the Orin's encodings (.SAT at bit 77, .RELU at 79, .FTZ at 80) and in Mesa NAK's HFMA2 layout. The fix registers 0x035 with HFMA2's emitter, which also covers the constant-bank and uniform forms. The MSL is identical to HFMA2's, so #1902's single-rounding rewrite applies to it as well, and the constant idiom comes out as a constant.
Making these ops run exposed one more bug, which this PR fixes since it's the same emitter.
.RELUon HFMA2, HFMA2.MMA and HMUL2 turned a NaN result into 0, but the GPU keeps the NaN (PTX's.relugives the canonical NaN). It's nowisnan(v) ? v : max(v, 0)on.RELUforms only.Reference entry: "HFMA2.MMA, the half-pair FMA on the tensor pipe" in
docs/reference/shaders.md.How to verify
On main, 17 fixture ops failed to translate because of HFMA2.MMA. With this PR:
hfma2,hfma2_sat,hfma2_reluhfma2_reluhad 314 NaN-to-0 lanes before the.RELUfixf2f_tf32,iadd64,isub64,imul64,imul24,idiv_u32,irem_s32,idiv_u32_by_7mufu_rcpmufu_rcp_ftz, so it joins the approximations listhfma2_ftz.FTZfix. With both PRs together it matches (332 of 2,048 halves, all NaN bit patterns), so whichever lands second should takehfma2_ftzout ofKNOWNfdiv_rn,f2i_s64,dadd,dmulKNOWNwith those reasonsNone of the HFMA2 cases shows #1902's double rounding: it's rare (70 in 2 million lanes on the Orin), and the fixture's 1,024 cases don't include one.
Not checked against the Orin: the constant-bank and uniform-register forms, which aren't in the fixture. With
.RELU, the select sits between the fma and the pack, so #1902's rewrite may not match those forms.Checked
test_dmsh_ampere_orin.py,test_dmsh_hmma.py; every othertest_dmsh_*gives the same result as on main (test_dmsh_ampere_mem.py,test_dmsh_meshstage.pyandtest_dmsh_pairs.pyfail on main the same way);test_nsp_chain.py,test_xlate_anycpu.py,test_docs.py.lint_python.pyshows no new findings.tool_lock.py --update-lockanddmsh_chain.py --headerwere run (chain ffb778cb19be).regress.py: not run. My only local Switch 2 build's shader package comes from an older shader split than main's map, so main's chain can't build it. I'll add a report once I have a fresh build.Docs
docs/reference/shaders.mdhas the entry, andpython3 dm/tools/docs_symptoms.pywas rundmsh_chain.py --headerwas run, anddmsh_chain.h, the translator dlls and the lock are part of the change