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F2FP packs bfloat16 for .BF16 and clamps negatives for .RELU (chain change) - #2046
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…re_orin.py runs about 190 operations, each the GPU compiler's own machine code for one PTX operation, through the translator, spirv-cross, the chain's MSL rewrites and Metal on this Mac's GPU, and compares every output word with what a Jetson Orin (sm_87) computed from the same 1,024 input rows. The translator tests checked the MSL a few encodings give, not the values; this one finds the FSETP.NE, SHFL lane, F2FP, rounding-mode and signed-zero differences the tracking issue lists, which KNOWN names until each fix takes its entry out. dm/gfx/tools/ampere_orin/capture.py records the fixture on any Linux machine with an Ampere GPU and NVIDIA's driver, with no toolkit or compiler on either side
…K_AB packed two f16s instead of two bfloat16s, and F2FP.RELU.PACK_AB kept negative values, because the translator read no format bit of F2FP but the merge one and always used packHalf2x16. .RELU (bit 75) now takes a negative float, -0 and -inf included, to +0 before the conversion and leaves a NaN alone; .BF16 (bit 76) rounds each float to its high 16 bits to nearest even with integer operations on its bits, which Metal's fast math keeps, and gives 0x7fff for a NaN, as the Jetson Orin does; the two together clamp first. test_dmsh_ampere_orin.py: f2fp_pack_bf16x2 differed in 1,827 of 2,048 halves and now in none, f2fp_pack_f16x2_relu in 843 and now only in 51 NaN bit patterns (a platform difference), and both leave KNOWN; the other translator tests are as on main; chain 7e5b543e0e15
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…ds#2046), with this branch's translator rebuilt from its own source; chain d04eb645fdbe
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Part of the Ampere accuracy series (#2040). It depends on #2041 for the test: the commits before this PR's own are #2041's and drop out once it lands, so this PR's own change is the last commit.
What and why
F2FP packs two floats into a pair (
cvt.rn.f16x2.f32and friends), and we ignored two of its flags:0xbfe7c0dc; we gave0xbf38c6de, which is those values as f16.AF2fpnow honours both. .RELU clamps each operand's bits to +0 when they're -0 through -inf, leaving NaN alone (the Orin keeps a NaN). .BF16 rounds to nearest even with integer operations on the float's bits,(bits + 0x7fff + ((bits >> 16) & 1)) >> 16, with a NaN giving0x7fffas the Orin does. Integer operations are exact under Metal's fast math. Combined, the clamp comes before the rounding. Plain F2FP and MERGE_C emit the same MSL as before. The cost is about 9 integer operations per half for .BF16 and two compares and a select per half for .RELU, and only on those forms.Reference entry: "F2FP's .BF16 and .RELU packs" in
docs/reference/shaders.md.How to verify
f2fp_pack_bf16x2f2fp_pack_f16x2_reluBoth come out of
KNOWN. The fixture has no case with .BF16 and .RELU together and no exact rounding tie, so those two paths rest on the code and on a model checked against every half of the fixture, not on the Orin directly.This overlaps #1800, which adds .RZ to F2FP.PACK_AB: both change the last line of
AF2fp. Whichever lands second should apply .RZ to the f16 pack that now takes the clamped operands. BF16 here always rounds to nearest even.Checked
test_dmsh_ampere_orin.py; every othertest_dmsh_*gives the same result as on main (test_dmsh_ampere_mem.py,test_dmsh_meshstage.pyandtest_dmsh_pairs.pyfail on main the same way);test_nsp_chain.py,test_xlate_anycpu.py,test_docs.py.lint_python.pyshows no new findings.tool_lock.py --update-lockanddmsh_chain.py --headerwere run (chain 7e5b543e0e15).regress.py: not run. My only local Switch 2 build's shader package comes from an older shader split than main's map, so main's chain can't build it. I'll add a report once I have a fresh build.Docs
docs/reference/shaders.mdhas the entry, andpython3 dm/tools/docs_symptoms.pywas rundmsh_chain.py --headerwas run, anddmsh_chain.h, the translator dlls and the lock are part of the change