Skip to content

mark vstl1_* functions as unsafe #2092

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft
folkertdev wants to merge 1 commit into
base: main
Choose a base branch
from
+38 −24
Draft

mark vstl1_* functions as unsafe #2092

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
56 changes: 34 additions & 22 deletions crates/core_arch/src/aarch64/neon/generated.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25421,107 +25421,119 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
pub unsafe fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
static_assert!(LANE == 0);
unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
pub unsafe fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
static_assert_uimm_bits!(LANE, 1);
unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
pub unsafe fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
static_assert!(LANE == 0);
unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
pub unsafe fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
static_assert_uimm_bits!(LANE, 1);
unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
pub unsafe fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
static_assert!(LANE == 0);
unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
pub unsafe fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
static_assert_uimm_bits!(LANE, 1);
unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val))
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
pub unsafe fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
static_assert!(LANE == 0);
let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
unsafe {
let lane: i64 = simd_extract!(val, LANE as u32);
(*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
}
let lane: i64 = simd_extract!(val, LANE as u32);
(*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
}
#[doc = "Store-Release a single-element structure from one lane of one register."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
#[doc = "## Safety"]
#[doc = " * Neon intrinsic unsafe"]
#[inline(always)]
#[target_feature(enable = "neon,rcpc3")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
#[rustc_legacy_const_generics(2)]
#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
#[cfg(target_has_atomic = "64")]
pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
pub unsafe fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
static_assert_uimm_bits!(LANE, 1);
let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
unsafe {
let lane: i64 = simd_extract!(val, LANE as u32);
(*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
}
let lane: i64 = simd_extract!(val, LANE as u32);
(*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
}
#[doc = "Subtract"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
Expand Down
6 changes: 4 additions & 2 deletions crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4459,7 +4459,8 @@ intrinsics:
doc: "Store-Release a single-element structure from one lane of one register."
arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
static_defs: ["const LANE: i32"]
safety: safe
safety:
unsafe: [neon]
Copy link
Copy Markdown
Contributor Author

@folkertdev folkertdev Apr 24, 2026 •
edited by rustbot
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@adamgemmell using neon here is not right, this is unsafe in its own right. I'm not sure if there are further safety conditions though, the link to the documentation that is generated for these functions does not work.

I also haven't quite reverse-engineered the right yaml to use to get a better message here.

View changes since the review

attr:
- FnCall: [target_feature, ['enable = "neon,rcpc3"']]
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
Expand Down Expand Up @@ -4488,7 +4489,8 @@ intrinsics:
doc: "Store-Release a single-element structure from one lane of one register."
arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
static_defs: ["const LANE: i32"]
safety: safe
safety:
unsafe: [neon]
attr:
- FnCall: [target_feature, ['enable = "neon,rcpc3"']]
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
Expand Down