riscv-rt: rename no-interrupts and no-exceptions to custom-interrupts and custom-exceptions

.github/workflows/clippy.yaml

@@ -29,8 +29,8 @@ jobs:
       - name: Run clippy (no features)
         run: cargo clippy --all --no-default-features -- -D warnings
       - name: Run clippy (all features)
-        # We exclude riscv-peripheral because it's not yet stable-compliant (added -A deprecated for pre_init macro)
-        run: cargo clippy --exclude riscv-peripheral --all --all-features -- -D warnings -A deprecated
+        # Added -A deprecated for pre_init macro and no-interrupts and no-exceptions features
+        run: cargo clippy --all --all-features -- -D warnings -A deprecated
 
   # Additonal clippy checks for riscv-rt
   clippy-riscv-rt:

.github/workflows/tests.yaml

@@ -54,13 +54,13 @@ jobs:
         run: RUSTFLAGS="-C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features device,memory
 
       - name: Build (custom interrupts and exceptions)
-        run: RUSTFLAGS="-C link-arg=-Tdevice.x -C link-arg=-Tmemory.x -C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features no-interrupts,no-exceptions
+        run: RUSTFLAGS="-C link-arg=-Tdevice.x -C link-arg=-Tmemory.x -C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features custom-interrupts,custom-exceptions
       - name: Build (custom interrupts and exceptions, include device.x)
-        run: RUSTFLAGS="-C link-arg=-Tmemory.x -C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features no-interrupts,no-exceptions,device
+        run: RUSTFLAGS="-C link-arg=-Tmemory.x -C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features custom-interrupts,custom-exceptions,device
       - name: Build (custom interrupts and exceptions, include memory.x)
-        run: RUSTFLAGS="-C link-arg=-Tdevice.x -C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features no-interrupts,no-exceptions,memory
+        run: RUSTFLAGS="-C link-arg=-Tdevice.x -C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features custom-interrupts,custom-exceptions,memory
       - name: Build (custom interrupts and exceptions, include device.x and memory.x)
-        run: RUSTFLAGS="-C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features no-interrupts,no-exceptions,device,memory
+        run: RUSTFLAGS="-C link-arg=-Tlink.x" cargo build --package tests-build --target ${{ matrix.target }} --example ${{ matrix.example }} --features custom-interrupts,custom-exceptions,device,memory
 
   # Job to check that all the builds succeeded
   tests-check:

riscv-rt/CHANGELOG.md

@@ -15,6 +15,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Deprecate `no-interrupts` feature in favor of `custom-interrupts`
+- Deprecate `no-exceptions` feature in favor of `custom-exceptions`
 - `_setup_interrupts` can now optionally receive an `usize` input argument
   with the ID of the running hart. This allows users to implement hart-specific
   interrupt setup in multi-hart targets.

riscv-rt/Cargo.toml

@@ -39,12 +39,14 @@ riscv = { path = "../riscv", version = "0.16.0", features = ["critical-section-s
 pre-init = []
 post-init = []
 custom-setup-interrupts = []
+custom-interrupts = []
+custom-exceptions = []
 s-mode = ["riscv-macros/s-mode"]
 single-hart = []
 v-trap = ["riscv/rt-v-trap", "riscv-macros/rt-v-trap"]
 u-boot = ["riscv-macros/rvrt-u-boot", "single-hart"]
-no-interrupts = []
-no-exceptions = []
+no-interrupts = ["custom-interrupts"] # deprecated, use `custom-interrupts` instead
+no-exceptions = ["custom-exceptions"] # deprecated, use `custom-exceptions` instead
 no-mhartid = ["single-hart"]
 no-xie-xip = []
 no-xtvec = []

riscv-rt/build.rs

@@ -14,13 +14,13 @@ fn add_linker_script(arch_width: u32) -> io::Result<()> {
     // Get target-dependent linker configuration and replace ${INCLUDE_LINKER_FILES} with it
     let mut include_content = String::new();
 
-    // If no-exceptions is disabled, include the exceptions.x files
-    if env::var_os("CARGO_FEATURE_NO_EXCEPTIONS").is_none() {
+    // If custom-exceptions is disabled, include the exceptions.x files
+    if env::var_os("CARGO_FEATURE_CUSTOM_EXCEPTIONS").is_none() {
         let exceptions_content = fs::read_to_string("exceptions.x")?;
         include_content.push_str(&(exceptions_content + "\n"));
     }
-    // If no-interrupts is disabled, include the interrupts.x files
-    if env::var_os("CARGO_FEATURE_NO_INTERRUPTS").is_none() {
+    // If custom-interrupts is disabled, include the interrupts.x files
+    if env::var_os("CARGO_FEATURE_CUSTOM_INTERRUPTS").is_none() {
         let interrupts_content = fs::read_to_string("interrupts.x")?;
         include_content.push_str(&(interrupts_content + "\n"));
     }
@@ -74,10 +74,10 @@ fn main() {
         println!("cargo:rerun-if-env-changed=RISCV_RT_BASE_ISA");
         println!("cargo:rerun-if-env-changed=RISCV_RT_LLVM_ARCH_PATCH");
         if env::var_os("CARGO_FEATURE_V_TRAP").is_some()
-            && env::var_os("CARGO_FEATURE_NO_INTERRUPTS").is_none()
+            && env::var_os("CARGO_FEATURE_CUSTOM_INTERRUPTS").is_none()
         {
             // This environment variable is used by the `#[riscv::pac_enum()]` call in
-            // `src/interrupts.rs` (when `v-trap` is enabled and `no-interrupts` disabled).
+            // `src/interrupts.rs` (when `v-trap` is enabled and `custom-interrupts` disabled).
             println!("cargo:rerun-if-env-changed=RISCV_MTVEC_ALIGN");
         }
 

riscv-rt/exceptions.x

@@ -1,7 +1,7 @@
 /* # EXCEPTION HANDLERS DESCRIBED IN THE STANDARD RISC-V ISA
 
-   If the `no-exceptions` feature is DISABLED, this file will be included in link.x.in.
-   If the `no-exceptions` feature is ENABLED, this file will be ignored.
+   If the `custom-exceptions` feature is DISABLED, this file will be included in link.x.in.
+   If the `custom-exceptions` feature is ENABLED, this file will be ignored.
 */
 
 /* It is possible to define a special handler for each exception type.

riscv-rt/interrupts.x

@@ -1,7 +1,7 @@
 /* # CORE INTERRUPT HANDLERS DESCRIBED IN THE STANDARD RISC-V ISA
 
-   If the `no-interrupts` feature is DISABLED, this file will be included in link.x.in.
-   If the `no-interrupts` feature is ENABLED, this file will be ignored.
+   If the `custom-interrupts` feature is DISABLED, this file will be included in link.x.in.
+   If the `custom-interrupts` feature is ENABLED, this file will be ignored.
 */
 
 /* It is possible to define a special handler for each interrupt type.

riscv-rt/src/exceptions.rs

@@ -9,7 +9,7 @@
 //!
 //! If your target has custom exception sources, the target PAC might provide equivalent
 //! code to adapt for the target needs. In this case, you may need to opt out this module.
-//! To do so, activate the `no-exceptions` feature of the `riscv-rt` crate.
+//! To do so, activate the `custom-exceptions` feature of the `riscv-rt` crate.
 
 use crate::TrapFrame;
 

riscv-rt/src/interrupts.rs

@@ -14,7 +14,7 @@
 //!
 //! If your target has custom core interrupt sources, the target PAC might provide equivalent code
 //! to adapt for the target needs (and is responsible for any alignment constraint). In this case,
-//! you may need to opt out this module. To do so, activate the `no-interrupts` feature of the
+//! you may need to opt out this module. To do so, activate the `custom-interrupts` feature of the
 //! `riscv-rt` crate.
 
 #[riscv::pac_enum(unsafe CoreInterruptNumber)]

riscv-rt/src/lib.rs

@@ -582,12 +582,12 @@
 //!
 //! Skips disabling interrupts (to support chips without XIE/XIP CSRs).
 //!
-//! ## `no-interrupts`
+//! ## `custom-interrupts`
 //!
 //! Opts out of the default implementation for `_dispatch_core_interrupt` to support platforms
 //! with custom core interrupt sources.
 //!
-//! ## `no-exceptions`
+//! ## `custom-exceptions`
 //!
 //! Opts out of the default implementation for `_dispatch_exception` to support platforms
 //! with custom exception sources.
@@ -683,13 +683,37 @@
 #![no_std]
 #![deny(missing_docs)]
 
+/// Backwards-compatibility deprecation warnings for renamed feature `no-interrupts`.
+/// If a user enables the old feature, emit a warning pointing them to the new `custom-interrupts`.
+#[cfg(feature = "no-interrupts")]
+#[deprecated(note = "feature `no-interrupts` is deprecated; use `custom-interrupts` instead")]
+pub const __RISCV_RT_DEPRECATED_NO_INTERRUPTS: () = ();
+
+#[cfg(feature = "no-interrupts")]
+#[allow(clippy::let_unit_value)]
+const _: () = {
+    let _ = __RISCV_RT_DEPRECATED_NO_INTERRUPTS;
+};
+
+/// Backwards-compatibility deprecation warnings for renamed feature `no-exceptions`.
+/// If a user enables the old feature, emit a warning pointing them to the new `custom-exceptions`.
+#[cfg(feature = "no-exceptions")]
+#[deprecated(note = "feature `no-exceptions` is deprecated; use `custom-exceptions` instead")]
+pub const __RISCV_RT_DEPRECATED_NO_EXCEPTIONS: () = ();
+
+#[cfg(feature = "no-exceptions")]
+#[allow(clippy::let_unit_value)]
+const _: () = {
+    let _ = __RISCV_RT_DEPRECATED_NO_EXCEPTIONS;
+};
+
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 mod asm;
 
-#[cfg(not(feature = "no-exceptions"))]
+#[cfg(not(feature = "custom-exceptions"))]
 pub mod exceptions;
 
-#[cfg(not(feature = "no-interrupts"))]
+#[cfg(not(feature = "custom-interrupts"))]
 pub mod interrupts;
 
 #[cfg(feature = "s-mode")]
@@ -838,13 +862,13 @@ pub struct TrapFrame {
 /// Targets that comply with the RISC-V standard can use the implementation provided
 /// by this crate in the [`exceptions`] module. Targets with special exception sources
 /// may provide their custom implementation of the `_dispatch_exception` function. You may
-/// also need to enable the `no-exceptions` feature to op-out the default implementation.
+/// also need to enable the `custom-exceptions` feature to op-out the default implementation.
 ///
 /// In direct mode (i.e., `v-trap` feature disabled), interrupt dispatching is performed
 /// by an extern `_dispatch_core_interrupt` function. Targets that comply with the RISC-V
 /// standard can use the implementation provided by this crate in the [`interrupts`] module.
 /// Targets with special interrupt sources may provide their custom implementation of the
-/// `_dispatch_core_interrupt` function. You may also need to enable the `no-interrupts`
+/// `_dispatch_core_interrupt` function. You may also need to enable the `custom-interrupts`
 /// feature to op-out the default implementation.
 ///
 /// In vectored mode (i.e., `v-trap` feature enabled), interrupt dispatching is performed

tests-build/Cargo.toml

@@ -14,5 +14,5 @@ single-hart = ["riscv-rt/single-hart"]
 v-trap = ["riscv-rt/v-trap"]
 device = ["riscv-rt/device"]
 memory = ["riscv-rt/memory"]
-no-exceptions = ["riscv-rt/no-exceptions"]
-no-interrupts = ["riscv-rt/no-interrupts"]
+custom-exceptions = ["riscv-rt/custom-exceptions"]
+custom-interrupts = ["riscv-rt/custom-interrupts"]

tests-build/src/lib.rs

@@ -9,10 +9,10 @@ pub enum ExternalInterrupt {
     I2c = 2,
 }
 
-#[cfg(not(feature = "no-interrupts"))]
+#[cfg(not(feature = "custom-interrupts"))]
 pub use riscv::interrupt::Interrupt as CoreInterrupt;
 
-#[cfg(feature = "no-interrupts")]
+#[cfg(feature = "custom-interrupts")]
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
 #[riscv::pac_enum(unsafe CoreInterruptNumber)]
 pub enum CoreInterrupt {
@@ -21,10 +21,10 @@ pub enum CoreInterrupt {
     MachineExternal = 11,
 }
 
-#[cfg(not(feature = "no-exceptions"))]
+#[cfg(not(feature = "custom-exceptions"))]
 pub use riscv::interrupt::Exception;
 
-#[cfg(feature = "no-exceptions")]
+#[cfg(feature = "custom-exceptions")]
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
 #[riscv::pac_enum(unsafe ExceptionNumber)]
 pub enum Exception {

tests-trybuild/Cargo.toml

@@ -6,7 +6,7 @@ edition = "2021"
 [dependencies]
 riscv = { path = "../riscv" }
 riscv-macros = { path = "../riscv-macros" }
-riscv-rt = { path = "../riscv-rt", features = ["no-exceptions", "no-interrupts", "post-init"] }
+riscv-rt = { path = "../riscv-rt", features = ["custom-exceptions", "custom-interrupts", "post-init"] }
 trybuild = "1.0"
 
 [features]