Enable suggested SAE Rust lints

.github/workflows/build.yml

@@ -14,7 +14,7 @@ jobs:
     steps:
       - id: set-matrix
         run: |
-          echo 'rust_versions=["stable", "1.83"]' >> "$GITHUB_OUTPUT"
+          echo 'rust_versions=["stable", "1.85"]' >> "$GITHUB_OUTPUT"
           echo 'stable_targets=["armv7a-none-eabi","armv7a-none-eabihf","armv7r-none-eabi","armv7r-none-eabihf","armv8r-none-eabihf"]' >> "$GITHUB_OUTPUT"
 
   # Build the workspace for a target architecture
@@ -26,9 +26,9 @@ jobs:
         rust: ${{ fromJSON(needs.setup.outputs.rust-versions) }}
         target: ${{ fromJSON(needs.setup.outputs.stable-targets) }}
         exclude:
-          - rust: 1.83
+          - rust: 1.85
             target: armv7a-none-eabihf
-          - rust: 1.83
+          - rust: 1.85
             target: armv8r-none-eabihf
     steps:
       - name: Checkout
@@ -63,9 +63,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2026-02-26
-          rustup component add rust-src --toolchain nightly-2026-02-26
-          rustup default nightly-2026-02-26
+          rustup install stable
+          rustup default stable
+          rustup component add rust-src
       - name: Build
         run: |
           just build-tier3 ${{ matrix.target }}
@@ -89,9 +89,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2026-02-26
-          rustup component add rust-src --toolchain nightly-2026-02-26
-          rustup default nightly-2026-02-26
+          rustup install stable
+          rustup default stable
+          rustup component add rust-src
       - name: Build
         run: |
           just build-tier3-no-atomics ${{ matrix.target }}
@@ -132,9 +132,9 @@ jobs:
         rust: ${{ fromJSON(needs.setup.outputs.rust-versions) }}
         target: ${{ fromJSON(needs.setup.outputs.stable-targets) }}
         exclude:
-          - rust: 1.83
+          - rust: 1.85
             target: armv7a-none-eabihf
-          - rust: 1.83
+          - rust: 1.85
             target: armv8r-none-eabihf
     steps:
       - name: Checkout

Cargo.toml

@@ -11,4 +11,4 @@ members = [
   "aarch32-rt",
   "aarch32-rt-macros",
 ]
-resolver = "2"
+resolver = "3"

aarch32-cpu/CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 - Added `Iciallu` register which allows invalidating the instruction cache.
+- Bumped MSRV to v1.85 to allow switch to Edition 2024
 
 ## [aarch32-cpu v0.2.0]
 

aarch32-cpu/Cargo.toml

@@ -8,7 +8,7 @@ categories = [
     "no-std",
 ]
 description = "CPU support for AArch32 Arm Processors"
-edition = "2021"
+edition = "2024"
 keywords = [
     "arm",
     "cortex-a",
@@ -21,7 +21,7 @@ name = "aarch32-cpu"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
-rust-version = "1.83"
+rust-version = "1.85"
 version = "0.2.0"
 
 [dependencies]
@@ -51,11 +51,81 @@ serde = ["dep:serde", "arbitrary-int/serde"]
 check-asm = []
 
 [package.metadata.docs.rs]
-# This is a list of supported Tier 2 targets, as of latest stable
 targets = [
-    "armv7r-none-eabihf",
-    "armv7r-none-eabi",
-    "armv7a-none-eabihf",
+    "armebv7r-none-eabi",
+    "armebv7r-none-eabihf",
+    "armv4t-none-eabi",
+    "armv5te-none-eabi",
+    "armv6-none-eabi",
+    "armv6-none-eabihf",
     "armv7a-none-eabi",
-    "armv8r-none-eabihf"
+    "armv7a-none-eabihf",
+    "armv7r-none-eabi",
+    "armv7r-none-eabihf",
+    "armv8r-none-eabihf",
+    "thumbv4t-none-eabi",
+    "thumbv5te-none-eabi",
+    "thumbv6-none-eabi",
+    "thumbv7a-none-eabi",
+    "thumbv7a-none-eabihf",
+    "thumbv7r-none-eabi",
+    "thumbv7r-none-eabihf",
+    "thumbv8r-none-eabihf",
 ]
+cargo-args = ["-Z", "build-std"]
+
+[lints.rust]
+missing_docs = "warn" # Indicates missing documentation on public functions
+missing_abi = "warn" # Explicit ABI documents the assumptions of the code
+unsafe_op_in_unsafe_fn = "warn" # Satisfies the recommendation in section 4.3.1
+elided_lifetimes_in_paths = "warn" # Highlights confusing implicit use of types with lifetimes
+explicit_outlives_requirements = "warn" # Less explicit lifetime bounds improve readability
+macro_use-extern_crate = "warn" # obscures the source of identifiers
+meta_variable_misuse = "warn" # More macro quality checks outweigh potential false positives
+non-local-definitions = "warn" # Highlights outdated and confusing location of definitions
+redundant-lifetimes = "warn" # Highlights a mistake or unfinished code
+single-use-lifetimes = "warn" # Simplifies code, improving readability
+trivial-numeric-casts = "warn" # Simplifies code, improving readability
+unit-bindings = "warn" # Simplifies code, improving readability
+unnameable-types = "warn" # Highlights inconsistency in public interface
+unreachable-pub = "warn" # Highlights inconsistency in public interface
+variant-size-differences = "warn" # Highlights inefficient data structures
+rust-2018-compatibility = "warn"
+rust-2018-idioms = "warn"
+rust-2021-compatibility = "warn"
+rust-2024-compatibility = "warn"
+unused = { level = "warn", priority = -1 } # this group might overlap
+unused_results = "warn"
+unused-qualifications = "warn"
+unused-lifetimes = "warn"
+unused-import-braces = "warn"
+
+[lints.clippy]
+cast_lossless = "warn" # Indicates a more idiomatic way to replace the cast
+cast_possible_truncation = "warn"
+cast_possible_wrap = "warn"
+cast_ptr_alignment = "warn"
+cast_sign_loss = "warn" # Should be checked for and properly handled in safety related projects
+exit = "warn" # Calling exit directly is likely wrong in a safety related environment
+infinite_loop = "warn" # Indicates improper return type
+iter_over_hash_type = "warn" # Indicates unpredictable order
+invalid_upcast_comparisons = "warn" # Likely wrong code
+lossy_float_literal = "warn" # Indicates rounding error
+missing_errors_doc = "warn" # Indicates incomplete documentation
+missing_docs_in_private_items = "warn" # Undocumented internal items are not an option
+panic_in_result_fn = "warn" # Indicates unexpected behavior
+ptr_cast_constness = "warn"
+ref_as_ptr = "warn"
+transmute_ptr_to_ptr = "warn" # Safer alternative available
+redundant_type_annotations = "warn" # Simpler code, highlights special cases
+shadow_unrelated = "warn" # Unidiomatic and high-risk use of shadowing
+try_err = "warn" # Indicates non-idiomatic way to avoid return
+wildcard_enum_match_arm = "warn" # See section 4.4.21.3, clashes with non-exhaustive
+as_underscore = "warn"
+format_push_string = "warn" # Avoids extra allocation
+as_ptr_cast_mut = "deny" # Clear misuse with a better alternative
+let_underscore_must_use = "deny" # Prevents a shortcut to ignore must-use results
+missing_panics_doc = "deny" # Indicates missing panic documentation
+undocumented_unsafe_blocks = "deny" # Indicates missing "unsafe" reasoning
+wildcard_imports = "deny" # Indicates unconstrained symbol imports
+declare_interior_mutable_const = "deny" # Indicates common mistake

aarch32-cpu/README.md

@@ -29,7 +29,7 @@ If you need a driver for the Arm Generic Interrupt Controller, see
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.83.0 and up, as recorded
+This crate is guaranteed to compile on stable Rust 1.85.0 and up, as recorded
 by the `package.rust-version` property in `Cargo.toml`.
 
 Increasing the MSRV is not considered a breaking change and may occur in a

aarch32-cpu/build.rs

@@ -5,5 +5,5 @@
 //! Copyright (c) Ferrous Systems, 2025
 
 fn main() {
-    arm_targets::process();
+    _ = arm_targets::process();
 }

aarch32-cpu/src/asmv4.rs

@@ -66,7 +66,8 @@ pub fn core_id() -> u32 {
     r & 0x00FF_FFFF
 }
 
-#[no_mangle]
+/// LLVM intrinsic for memory barriers
+#[unsafe(no_mangle)]
 pub extern "C" fn __sync_synchronize() {
     // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block
     unsafe {

aarch32-cpu/src/asmv7.rs

@@ -7,7 +7,7 @@
 /// after the `DMB` instruction.
 #[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn dmb() {
-    use core::sync::atomic::{compiler_fence, Ordering};
+    use core::sync::atomic::{Ordering, compiler_fence};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("dmb", options(nostack, preserves_flags));
@@ -24,7 +24,7 @@ pub fn dmb() {
 ///  * all cache and branch predictor maintenance operations before this instruction complete
 #[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn dsb() {
-    use core::sync::atomic::{compiler_fence, Ordering};
+    use core::sync::atomic::{Ordering, compiler_fence};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("dsb", options(nostack, preserves_flags));
@@ -38,7 +38,7 @@ pub fn dsb() {
 /// from cache or memory, after the instruction has been completed.
 #[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn isb() {
-    use core::sync::atomic::{compiler_fence, Ordering};
+    use core::sync::atomic::{Ordering, compiler_fence};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("isb", options(nostack, preserves_flags));

aarch32-cpu/src/critical_section.rs

@@ -10,10 +10,10 @@ mod single_core {
     critical_section::set_impl!(SingleCoreCriticalSection);
 
     /// Indicates the critical section was entered with interrupts on
-    pub const INT_ON: u8 = 0;
+    const INT_ON: u8 = 0;
 
     /// Indicates the critical section was entered with interrupts off
-    pub const INT_OFF: u8 = 1;
+    const INT_OFF: u8 = 1;
 
     #[cfg(feature = "critical-section-single-core")]
     unsafe impl critical_section::Impl for SingleCoreCriticalSection {
@@ -23,11 +23,7 @@ mod single_core {
             let was_active = !crate::register::Cpsr::read().i();
             crate::interrupt::disable();
             atomic::compiler_fence(atomic::Ordering::SeqCst);
-            if was_active {
-                INT_ON
-            } else {
-                INT_OFF
-            }
+            if was_active { INT_ON } else { INT_OFF }
         }
 
         unsafe fn release(was_active: critical_section::RawRestoreState) {
@@ -52,18 +48,18 @@ mod multi_core {
     critical_section::set_impl!(MultiCoreCriticalSection);
 
     /// The default value for our spin-lock
-    pub const UNLOCKED: u32 = 0xFFFF_FFFF;
+    const UNLOCKED: u32 = 0xFFFF_FFFF;
 
     /// Indicates the critical section was entered with interrupts on, and the spin-lock unlocked
-    pub const INT_ON_UNLOCKED: u8 = 0;
+    const INT_ON_UNLOCKED: u8 = 0;
 
     /// Indicates the critical section was entered with interrupts off, and the spin-lock locked (by us)
-    pub const INT_OFF_LOCKED: u8 = 1;
+    const INT_OFF_LOCKED: u8 = 1;
 
     /// Indicates the critical section was entered with interrupts off, and the spin-lock unlocked
-    pub const INT_OFF_UNLOCKED: u8 = 2;
+    const INT_OFF_UNLOCKED: u8 = 2;
 
-    pub static CORE_SPIN_LOCK: core::sync::atomic::AtomicU32 =
+    static CORE_SPIN_LOCK: core::sync::atomic::AtomicU32 =
         core::sync::atomic::AtomicU32::new(UNLOCKED);
     unsafe impl critical_section::Impl for MultiCoreCriticalSection {
         unsafe fn acquire() -> critical_section::RawRestoreState {

aarch32-cpu/src/generic_timer/el0.rs

@@ -2,7 +2,7 @@
 
 use crate::register;
 
-/// Represents our Physical Timer when we are running at EL0.
+/// Represents our Generic Physical Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
@@ -75,11 +75,11 @@ impl super::GenericTimer for El0PhysicalTimer {
     }
 }
 
-/// Represents our Virtual Timer when we are running at EL0.
+/// Represents our Generic Virtual Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
-/// [El1PhysicalTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
+/// [El1VirtualTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
 pub struct El0VirtualTimer();
 
 impl El0VirtualTimer {

aarch32-cpu/src/generic_timer/el2.rs

@@ -161,7 +161,7 @@ impl El2HypPhysicalTimer {
     }
 }
 
-impl super::GenericTimer for El2HypPhysicalTimer {
+impl GenericTimer for El2HypPhysicalTimer {
     fn frequency_hz(&self) -> u32 {
         register::Cntfrq::read().0
     }

aarch32-cpu/src/interrupt.rs

@@ -1,6 +1,6 @@
 //! Interrupts on Arm AArch32
 
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 
 /// Enable interrupts
 ///