simple-risc-v

Simple RISC-V CPU in behavioral Verilog with functional simulation

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ALU.v		ALU.v
ALUController.v		ALUController.v
Controller.v		Controller.v
DataMem.v		DataMem.v
Datapath.v		Datapath.v
FlipFlop.v		FlipFlop.v
ImmGen.v		ImmGen.v
InstMem.v		InstMem.v
Mux.v		Mux.v
README.md		README.md
RegFile.v		RegFile.v
processor.v		processor.v

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