Jeff's Changes prior to Launch

docs/spec/isa1.mdx

@@ -0,0 +1,67 @@
+# The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
+
+Volume I of the RISC-V ISA describes the architecture of the users mode (space).
+
+*Latest version: 20250508    Date: May 2025*
+
+[HTML](https://developer.riscv.org/docs/reference/isa/unpriv/unpriv-index.html) | <br></br>[PDF](https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view?usp=drive_link)
+
+# **Details**
+
+| RISC-V Community: | [Unprivileged Horizontal Committee](https://lists.riscv.org/g/tech-unprivileged) |
+| :---- | :---- |
+| **Source:** | [riscv/riscv-isa-manual](https://github.com/riscv/riscv-isa-manual/) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 20250508 | May 2025 | [HTML](https://developer.riscv.org/docs/reference/isa/unpriv/unpriv-index.html), [PDF](https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view?usp=drive_link) |
+| 20240411 | April 2024 | [PDF](https://drive.google.com/file/d/1vI_P4f0kxzpJ6P1wQF9eRSvBmtcnGJkq/view?usp=drive_link) |
+| 20191213 | Dec. 2019 | [PDF](https://drive.google.com/file/d/1s0lZxUZaa7eV_O0_WsZzaurFLLww7ou5/view?usp=drive_link) |
+| 2.2 (Creative Commons) | May 2017 | [PDF](https://github.com/riscv/riscv-isa-manual/blob/eb86a900f418a5436b8e31abc0563be3cb402a16/release/riscv-spec-v2.2.pdf) |
+| 2.1 | May 2016 | [PDF](https://github.com/riscv/riscv-isa-manual/blob/eb86a900f418a5436b8e31abc0563be3cb402a16/release/riscv-spec-v2.1.pdf) |
+| 2.0 | May 2014 | [PDF](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf) |
+| Original | May 2011 | [PDF](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf) |
+
+# **Pending Updates**
+
+No extensions have been ratified but not included in a published specification.
+
+# **Archived Ratifications**
+
+The following documents were ratified and are included in the latest published specification.
+
+|   | Ratified | New extension(s) or Profile(s) |
+| :---- | :---: | :---- |
+
+|   | Ratified | New extension(s) or Profile(s) |
+| :---- | :---: | :---- |
+| **Load/Store Pair for RV32 (Zilsd & Zclsd)**  <br></br>[PDF](https://drive.google.com/file/d/1oMMxKJSuNKNcjiZdJEPeUqOCxr8VcxCn/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-zilsd) | February 2025 | Zilsd, Zclsd |
+| **Shadow Stacks and Landing Pads**  <br></br>[PDF](https://drive.google.com/file/d/1k8zkQAlfe8hjjqk3903N9tig5YId1-7S/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-cfi) | June 2024 | Zicfiss, Zicfilp |
+| **BF16 Extensions**  <br></br>[PDF](https://drive.google.com/file/d/1iwlVykLz2TuYsGLnMgNwGk4W58vdGBmc/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-bfloat16) | June 2024 | Zfbfmin, Zvfbfmin, Zvfbfwma |
+| **Zaamo and Zalrsc Extensions**  <br></br>[PDF](https://drive.google.com/file/d/1y2jMvCgnlPhFIe_MKv6NvSzxS-Jduz76/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-zaamo-zalrsc) | April 2024 | Zaamo, Zalrsc |
+| **B Standard Extension for Bit Manipulation Instructions**  <br></br>[PDF](https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-b) | April 2024 | B |
+| **Byte and Halfword Atomic Memory Operations (Zabha)**  <br></br>[PDF](https://drive.google.com/file/d/1OnM4q3BnAJ_HuGfuzVB7CSpbqZ5OVH8s/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-zabha) | April 2024 | Zabha |
+| **May-Be-Operations**  <br></br>[PDF](https://drive.google.com/file/d/17CxX1Fj6BpJH47AIk_hZo64wcj5LTjIk/view?usp=drive_link) | March 2024 | Zimop, Zcmop |
+| **RISC-V Integer Conditional (Zicond) operations extension**  <br></br>[PDF](https://drive.google.com/file/d/1ssWUkvSp_CCw6riw3ThSwJFKn4GH5QLM/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-zicond/releases/tag/v1.0.1) | November 2023 | Zicond |
+| **Atomic Compare-and-Swap (CAS) Instructions (Zacas)**  <br></br>[PDF](https://drive.google.com/file/d/1Bjfkepuh3m0V2EUqoUeGWQWfzJi9lpAp/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0) | November 2023 | Zacas |
+| **RISC-V Cryptography Extensions Volume II: Vector Instructions**  <br></br>[PDF](https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view?usp=sharing) , [Source](https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0) | September 2023 | Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt |
+| **"Zfa" Standard Extension for Additional Floating-Point Instructions**  <br></br>[PDF](https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view?usp=sharing) | September 2023 | Zfa |
+| **“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half-Precision Floating-Point Arithmetic**  <br></br>[PDF](https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view?usp=drive_link) | June 2023 | Zvfh, Zvfhmin |
+| **“Zihintntl” Non-Temporal Locality Hints**  <br></br>[PDF](https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view?usp=share_link) | May 2023 | Zihintntl |
+| **RISC-V Code Size Reduction**  <br></br>[PDF](https://drive.google.com/file/d/1zmWDmfbtVY9I6hn0vuLTbk5rsSPc44sL/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0) | April 2023 | Zca, Zcb, Zcd, Zce, Zcf, Zcmp, Zcmt |
+| **"Zicntr" and "Zihpm" Counters**  <br></br>[PDF](https://drive.google.com/file/d/1qa57pePesOiDOrNzxuuGFhCL4Rbi9AYB/view?usp=share_link) | March 2023 | Zicntr, Zihpm |
+| **RV32E and RV64E Base Integer Instruction Sets**  <br></br>[PDF](https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view?usp=share_link) | January 2023 | RV32E/RV64E |
+| **“Ztso” Standard Extension for Total Store Ordering**  <br></br>[PDF](https://drive.google.com/file/d/173BGJQLqtEzAAD5lV9uaLMMjS91WeAt7/view?usp=share_link) | January 2023 | Ztso |
+| **RISC-V Wait-on-Reservation-Set (Zawrs) extension**  <br></br>[PDF](https://drive.google.com/file/d/1wKk4dC_at8bFJRUwLR84fV3i1X9jwtAe/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-zawrs/releases/tag/v1.01) | November 2022 | Zawrs |
+| **Zmmul Extension**  <br></br>[PDF](https://drive.google.com/file/d/1v-mI2hikzI4swl0KNYPQ82VkTRt9uOPg/) | June 2022 | Zmmul |
+| **RISC-V Base Cache Management Operation ISA Extensions**  <br></br>[PDF](https://drive.google.com/file/d/1jfzhNAk7viz4t2FLDZ5z4roA0LBggkfZ/view?usp=drive_link) | November 2021 | Zicbom, Zicbop, Zicboz |
+| **RISC-V Bit-Manipulation ISA-extensions**  <br></br>[PDF](https://drive.google.com/file/d/11-dKxnp7yfl9L3HESXGCtYl90dFKGTzE/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0) | November 2021 | Zba, Zbb, Zbc, Zbs |
+| **RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions**  <br></br>[PDF](https://drive.google.com/file/d/1Thd010Eh2DqnhDHpDd3SM7Ame7KENkPw/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-crypto/releases/tag/v1.0.1-scalar) | November 2021 | Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, Zkr |
+| **RISC-V Vector Extension**  <br></br>[PDF](https://drive.google.com/file/d/1AQZ3l_EGeMa2NftMO562gVZ4vj61od2H/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-v-spec) | November 2021 | Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, Zv |
+| **"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point**  <br></br>[PDF](https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view?usp=sharing) | November 2021 | Zfh, Zfhmin |
+| **"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers**  <br></br>[PDF](https://drive.google.com/file/d/13nlRJq-kfAlKGKC7G_NR2RaJi3N2Xb6z/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-zfinx) | November 2021 | Zfinx, Zdinx, Zhinx, Zhinxmin |
+| **“Zihintpause” Pause Hint**  *[PDF*](https://drive.google.com/file/d/1WXT3TXZs0pwS9BgPoDesJQ61_0GVSQpZ/view?usp=drive_link) | February 2021 | Zihintpause |

docs/spec/isa2.mdx

@@ -0,0 +1,65 @@
+# The RISC-V Instruction Set Manual Volume II: Privileged ISA
+
+Volume II of the RISC-V ISA describes the architecture of the supervisor and machine modes (space).
+
+*Latest version: 20250508    Date: May 2025*
+
+[HTML](https://developer.riscv.org/docs/reference/isa/priv/priv-index.html) | [PDF](https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view?usp=drive_link)
+
+# **Details**
+
+| RISC-V Community: | [Privileged Horizontal Committee](https://lists.riscv.org/g/tech-privileged) |
+| :---- | :---- |
+| **Source:** | [riscv/riscv-isa-manual](https://github.com/riscv/riscv-isa-manual/) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 20250508 | May 2025 | [HTML](https://developer.riscv.org/docs/reference/isa/priv/priv-index.html), [PDF](https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view?usp=drive_link) |
+| 20240411 | April 2024 | [PDF](https://drive.google.com/file/d/1RQRncRGhqcwiYJb5Bp9DiWbVXnSrEPvz/view?usp=drive_link) |
+| 20211203 | December 2021 | [PDF](https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view?usp=drive_link) |
+| 1.11 | June 2019 | [PDF](https://drive.google.com/file/d/1ateuJOBQyL7d8Zbs_15G_O9C_NdAxxZe/view?usp=drive_link) |
+| 1.10 | May 2017 | [PDF](https://github.com/riscv/riscv-isa-manual/blob/eb86a900f418a5436b8e31abc0563be3cb402a16/release/riscv-privileged-v1.10.pdf) |
+| 1.9 | July 2016 | [PDF](https://github.com/riscv/riscv-isa-manual/blob/eb86a900f418a5436b8e31abc0563be3cb402a16/release/riscv-privileged-v1.9.pdf) |
+| 1.7 | May 2015 | [PDF](https://github.com/riscv/riscv-isa-manual/blob/eb86a900f418a5436b8e31abc0563be3cb402a16/release/riscv-privileged-v1.7.pdf) |
+
+# **Pending Updates**
+
+The following extensions have been ratified but not yet included in a published specification.
+
+|   | Ratified | New extension(s) |
+| :---- | :---: | :---- |
+| PTE Reserved-for-Software Bits 60-59  <br></br>[PDF](https://drive.google.com/file/d/1l6Lq0oI152gd4YgBv0Hg-3YdoGRWPFjM/view?usp=sharing) , [Source](https://github.com/riscv/riscv-isa-manual/pull/2241) | August 2025 | Svrsw60t59b |
+| *The RISC-V Debug Specification*  <br></br>[PDF](https://drive.google.com/file/d/1h_f9NgB_8m2fS6uCnKP1Oho-3x1MpBEl/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-debug-spec) | February 2025 | Sdext, Sdtrig |
+| *RISC-V Advanced Interrupt Architecture*  <br></br>[PDF](https://drive.google.com/file/d/1joBC2hWGEHJL4tFabjcqMpRqQNkqJ5WR/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-aia) | June 2023 | Smaia, Ssaia |
+
+# **Archived Ratifications**
+
+The following documents were ratified and are included in the latest published specification.
+
+|   | Ratified | New extension(s) or Profile(s) |
+| :---- | :---: | :---- |
+
+|   | Ratified | New extension(s) or Profile(s) |
+| :---- | :---: | :---- |
+| **RISC-V Control Transfer Records**  <br></br>[PDF](https://drive.google.com/file/d/17P5RMSU3Ta-8sTdwr5dr-UyVEn13HWWN/view?usp=sharing) , [Source](https://github.com/riscv/riscv-control-transfer-records) | November 2024 | Smctr, Ssctr |
+| **RISC-V Pointer Masking**  <br></br>[PDF](https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-j-extension) | October 2024 | Smmpm, Smnpm, Ssnpm, Supm, Sspm |
+| **The RISC-V Instruction Set Manual Volume II: Privileged Architecture (Priv 1.13)  ** <br></br>[PDF](https://drive.google.com/file/d/1GGwOGJvyV59g1YOko6ut__dVlKTCVthJ/view?usp=drive_link) | October 2024 | Sm1p13, Ss1p13 |
+| **Double Trap**  <br></br>[PDF](https://drive.google.com/file/d/1e5-3pUdh_UcVmKlwxO6KBNVHivMXGdOf/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-double-trap) | August 2024 | Ssdbltrp, Smdbltrp |
+| **RISC-V Quality-of-Service (QoS) Identifiers**  <br></br>[PDF](https://drive.google.com/file/d/1KO5iHq1g7dW3L6logUtY0vgTfQFBlg4V/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-ssqosid) | June 2024 | Ssqosid |
+| **Obviating Memory-Management Instructions after Marking PTEs Valid**  <br></br>[PDF](https://drive.google.com/file/d/1D1ZvAvSigDkazmRdpVE35IiPQpyj3J8D/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-svvptc) | June 2024 | Svvptc |
+| **Resumable Non-Maskable Interrupts**  <br></br>[PDF](https://drive.google.com/file/d/1tNQPe6kXFgI9FYmsn94G7X4zAA6cZGEo/view?usp=drive_link) | June 2024 | Smrnmi |
+| **RISC-V Supervisor Counter Delegation**  <br></br>[PDF](https://drive.google.com/file/d/1qFcNKToo8E2jjkubXi_70SclHuEzba5N/view?usp=drive_link) , [Source](https://github.com/riscv/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0) | March 2024 | Smcdeleg, Ssccfg |
+| **RISC-V Indirect CSR Access (Smcsrind/Sscsrind)**  <br></br>[PDF](https://drive.google.com/file/d/17MxYRvoOiQqtdfSCPw_SskJtXVEbi1jR/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0) | February 2024 | Smcsrind, Sscsrind |
+| **Hardware Updating of PTE A/D Bits (Svadu)**  <br></br>[PDF](https://drive.google.com/file/d/1-5kz8_9zg8wYcY-zyLdyBp8j12PuxmlG/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-svadu/releases/tag/v1.0) | November 2023 | Svadu |
+| **RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf)**  <br></br>[PDF](https://drive.google.com/file/d/1T33-7wnEo8Lar3n0k33ejW7_cROt0H0k/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-smcntrpmf/releases/tag/v1.0) | November 2023 | Smcntrpmf |
+| **RISC-V Advanced Interrupt Architecture**  <br></br>[PDF](https://drive.google.com/file/d/16life2Y5u7Plebbl4v1fFM1-NK-KHw0Y/view?usp=sharing) , [Source](https://github.com/riscv/riscv-aia/releases/tag/1.0) | June 2023 | Smaia, Ssaia |
+| **PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)**  <br></br>[PDF](https://drive.google.com/file/d/1karAdJDKYReW-TtOygh0JD5r65Pygx0e/view?usp=drive_link) | November 2021 | Smepmp |
+| **RISC-V Privileged Architecture 1.12**  <br></br>[PDF](https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view?usp=drive_link) | November 2021 | Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt |
+| **RISC-V Count Overflow and Mode-Based Filtering Extension**  <br></br>[PDF](https://drive.google.com/file/d/1RiAIOVoN1E7bv6_kEzcgATkhbeUdqu5t/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-count-overflow/releases/tag/v0.5.2) | November 2021 | Sscofpmf |
+| **RISC-V State Enable Extension**  <br></br>[PDF](https://drive.google.com/file/d/1dhI6OzVbejQbfwyBTuwK9U4VUmW8ii4o/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-state-enable/releases/tag/v1.0.0) | November 2021 | Smstateen |
+| **RISC-V "stimecmp / vstimecmp" Extension**  <br></br>[PDF](https://drive.google.com/file/d/1O0ogDHijAc7gM58Byb0BRqIRGYsdOt2D/view?usp=drive_link) , [Source](https://github.com/riscvarchive/riscv-time-compare/releases/tag/v0.5.4) | November 2021 | Sstc |
+

docs/spec/non-isa/abi.md

@@ -4,8 +4,25 @@ id: abi
 hide_table_of_contents: true
 pdf: /pdf/riscv-abi.pdf
 ---
+# RISC-V ABIs Specification
 
 Provides the processor-specific application binary interface document for RISC-V.
 
-<PDF download= {frontMatter.pdf} title= {frontMatter.title} >
-</PDF>
+*Latest version: 1.0    Date: November 2022*
+
+[PDF](https://drive.google.com/file/d/1Ja_Tpp_5Me583CGVD-BIZMlgGBnlKU4R/view?usp=drive_link)
+
+# **Details**
+
+| RISC-V Community: | [Application & Tools Horizontal Committee](https://lists.riscv.org/g/apps-tools-software) |
+| :---- | :---- |
+| **Source:** | [riscv-non-isa/riscv-elf-psabi-doc](https://github.com/riscv-non-isa/riscv-elf-psabi-doc) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 1.0 | November 2022 | [PDF](https://drive.google.com/file/d/1Ja_Tpp_5Me583CGVD-BIZMlgGBnlKU4R/view?usp=drive_link) |
+

docs/spec/non-isa/advanced-interrupt.mdx

@@ -4,8 +4,24 @@ id: advanced-interrupt
 hide_table_of_contents: true
 pdf: /pdf/riscv-interrupts.pdf
 ---
+# RISC-V Advanced Interrupt Architecture
 
 Describes an Advanced Interrupt Architecture for RISC-V systems.
 
-<PDF download= {frontMatter.pdf} title= {frontMatter.title} >
-</PDF>
+*Latest version: 1.0    Date: June 2023*
+
+[PDF](https://drive.google.com/file/d/16life2Y5u7Plebbl4v1fFM1-NK-KHw0Y/view?usp=sharing)
+
+# **Details**
+
+| RISC-V Community: | [Privileged Software Horizontal Committee](https://lists.riscv.org/g/privileged-software) |
+| :---- | :---- |
+| **Source:** | [riscv/riscv-aia](https://github.com/riscv/riscv-aia) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 1.0 | June 2023 | [PDF](https://drive.google.com/file/d/16life2Y5u7Plebbl4v1fFM1-NK-KHw0Y/view?usp=sharing) |

docs/spec/non-isa/brs.mdx

@@ -0,0 +1,27 @@
+---
+title: Boot and Runtime Services Specification
+id: brs
+hide_table_of_contents: true
+pdf: /pdf/riscv-brs.pdf
+---
+RISC-V Boot and Runtime Services Specification (BRS)
+
+Defines a standardized set of software capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in an implementation to utilize in acts of device discovery, OS boot and hand-off, system management, and other operations.
+
+*Latest version: 1.0    Date: August 2025*
+
+[PDF](https://drive.google.com/file/d/1ZvEa5AX3j7FXmXW5H1chIMVkyjJGmFmh/view?usp=sharing)
+
+# **Details**
+
+| RISC-V Community: | [Privileged Software Horizontal Committee](https://lists.riscv.org/g/privileged-software) |
+| :---- | :---- |
+| **Source:** | [riscv-non-isa/riscv-brs](https://github.com/riscv-non-isa/riscv-brs) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 1.0 | August 2025 | [PDF](https://drive.google.com/file/d/1ZvEa5AX3j7FXmXW5H1chIMVkyjJGmFmh/view?usp=sharing) |