GitHub - rinderer/rtl: RTL sources for OpTiMSoC · GitHub

Name		Name	Last commit message	Last commit date
bootrom		bootrom
cdc		cdc
clockmanager		clockmanager
compute_tile_dm		compute_tile_dm
compute_tile_pgas		compute_tile_pgas
debug_system		debug_system
fifo_dbg_if		fifo_dbg_if
lisnoc/scripts		lisnoc/scripts
memory_tile_dm		memory_tile_dm
memory_tile_pgas		memory_tile_pgas
mor1kx		mor1kx
mor1kx_module		mor1kx_module
networkadapter_ct		networkadapter_ct
noclsu		noclsu
or1200_module		or1200_module
or1200mp		or1200mp
soccerboard_tile/verilog		soccerboard_tile/verilog
sram		sram
system_2x2_cccc_dm		system_2x2_cccc_dm
system_2x2_cccm_dm		system_2x2_cccm_dm
system_2x2_ccmc_pgas/verilog		system_2x2_ccmc_pgas/verilog
system_4x4_c_dm/verilog		system_4x4_c_dm/verilog
system_irobot_pgas/verilog		system_irobot_pgas/verilog
system_simpledemo_pgas		system_simpledemo_pgas
trace_monitor		trace_monitor
uart_tile/verilog		uart_tile/verilog
wb_cas_unit		wb_cas_unit
wb_interconnect		wb_interconnect
xilinx_ddr		xilinx_ddr
.gitignore		.gitignore
optimsoc_functions.vh		optimsoc_functions.vh

About

RTL sources for OpTiMSoC

0 stars

1 watching

Report repository

Releases

Packages

Contributors

Languages