hw: GLSU bug fixes and cleanup

Makefile

@@ -189,7 +189,7 @@ riscv_unit_tests:
 	autoconf && \
 	./configure target_alias=${GCC_INSTALL_DIR}/bin/riscv64-unknown-elf --prefix=${RISCV_TESTS_INSTALL_DIR}/target && \
 	cd env/p && git apply ../../../patches/eoc.patch &&\
-	cd ../../../ && make riscv_tests_compile))
+	cd ../../../ && make riscv_tests_standard))
 
 # Helper targets
 .PHONY: clean

apps/Makefile

@@ -30,6 +30,7 @@ include $(COMMON_DIR)/default_args.mk
 nr_clusters ?= 2
 
 include $(COMMON_DIR)/runtime.mk
+include rivec.mk
 
 APPS := $(patsubst $(APPS_DIR)/%/main.c,%,$(wildcard $(APPS_DIR)/*/main.c))
 
@@ -51,7 +52,7 @@ bin/fft:  ENV_DEFINES += -DFFT_SAMPLES=$(subst ",,$(firstword $(def_args_fft)))
 bin/fft%: ENV_DEFINES += -DFFT_SAMPLES=$(subst ",,$(firstword $(def_args_fft)))
 endif
 
-all: $(BINARIES)
+all: apps_binaries riscv_tests rivec_binaries
 
 # Pre-process the linker-script to correclty align the sections
 .PHONY: linker_script
@@ -62,7 +63,9 @@ linker_script: $(COMMON_DIR)/script/align_sections.sh $(ROOT_DIR)/../../config/$
 
 # Make all applications
 $(APPS): % : bin/% $(APPS_DIR)/Makefile $(shell find common -type f)
-.PHONY: $(BINARIES)
+.PHONY: apps_binaries
+
+apps_binaries: $(BINARIES)
 
 # Patch spike crt0 to enable vector extension before execution
 .PHONY: patch-spike-crt0
@@ -114,8 +117,6 @@ bin/$1: $1/data.S.o $(addsuffix .o, $(shell find $(1) -name "*.c" -o -name "*.S"
 endef
 $(foreach app,$(APPS),$(eval $(call app_compile_template,$(app))))
 
-include rivec.mk
-
 # Make the RISC-V tests
 riscv_tests: $(CVA6_BINARIES) $(ARA_BINARIES)
 
@@ -174,8 +175,8 @@ riscv_tests_spike_clean:
 	make -C riscv-tests/isa clean
 
 # Compile Standardized RISC-V tests
-.PHONY: riscv_tests_compile
-riscv_tests_compile:
+.PHONY: riscv_tests_standard
+riscv_tests_standard:
 	cd riscv-tests && \
 	make benchmarks && make isa -i
 

apps/README.md

@@ -3,6 +3,15 @@
 This folder contains the benchmarks, programs, and tests ready to be run on AraXL.
 All software sources are licensed under [Apache 2.0](../LICENSE.sw).
 
+1) Synthetic benchmarks such as `fmatmul`, `fconv2d` in this `apps/` folder
+2) Custom RISC-V tests in `rvv-tests/`
+3) RiVEC benchmarks as a git submodule `riscv-vectorized-benchmark-suite/` modified to run on the araxl baremetal environment
+
+To compile all tests and benchmarks
+```bash
+make all nr_clusters=2
+```
+
 SW utilities and benchmarks for AraXL using external contributions,
 * `RiVEC` - Use of the RISC-V VECTOR intrinsics mapping `common/rivec/vector_defines.h` and benchmarks `apps/cos`, `apps/log`, `apps/exp` by Cristóbal Ramírez Lazo, "Barcelona 2019" under [license](common/rivec/LICENSE)
 * `print` - `common/printf.c`, `common/printf.h` Print primitives for embedded systems under the MIT License (MIT)
@@ -44,15 +53,15 @@ Example:
 
 ```bash
 cd apps
-make bin/fconv2d OUT_MTX_SIZE=112 F_SIZE=7
+make bin/fconv2d def_args_fconv2d="64 64 7"
 ```
 
 ### Standard RISC-V tests
 
 To compile the standardized riscv tests from https://github.com/riscv/riscv-tests
 ```bash
 cd apps
-make riscv_tests_compile
+make riscv_tests_standard
 ```
 
 ### RISC-V vector tests

hardware/src/ara_dispatcher.sv

@@ -526,8 +526,13 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                     automatic int unsigned vl_rem = vl_tot & ((1 << num_clusters_i << $clog2(NrLanes)) - 1);
                     automatic int unsigned vl_base = (vl_tot & ('1 << (num_clusters_i + $clog2(NrLanes)))) >> num_clusters_i;
                     automatic int unsigned vl_rem_diff = vl_rem - (cluster_id_i * NrLanes);
-                    vl_d = ((vl_tot >> num_clusters_i) >= vlmax) ? vlmax : vl_base;
-                    vl_d += (vl_rem >= (cluster_id_i+1) * NrLanes) ? NrLanes : (vl_rem >= (cluster_id_i * NrLanes)) ? vl_rem_diff : '0;
+                    if ((vl_tot >> num_clusters_i) >= vlmax) begin
+                      vl_d = vlmax;
+                    end else begin
+                      vl_d = vl_base;
+                      vl_d += (vl_rem >= (cluster_id_i+1) * NrLanes) ? NrLanes :
+                              (vl_rem >= (cluster_id_i * NrLanes)) ? vl_rem_diff : '0;
+                    end
                     vl_cluster_d = (vl_tot >= vlmax_cluster) ? vlmax_cluster : vl_tot;
                   end else begin // vsetvl || vsetvli
                     if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd == '0) begin
@@ -544,9 +549,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                       automatic int unsigned vl_rem = vl_tot & ((1 << num_clusters_i << $clog2(NrLanes)) - 1);
                       automatic int unsigned vl_base = (vl_tot & ('1 << (num_clusters_i + $clog2(NrLanes)))) >> num_clusters_i;
                       automatic int unsigned vl_rem_diff = vl_rem - (cluster_id_i * NrLanes);
-                      vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_cluster_d)]) || (vl_tot >= vlmax_cluster)) ? vlmax : vl_base;
-                      vl_d += (vl_rem >= (cluster_id_i+1) * NrLanes) ? NrLanes : (vl_rem >= (cluster_id_i * NrLanes)) ? vl_rem_diff : '0;
-                      vl_cluster_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_cluster_d)]) || (vl_tot >= vlmax_cluster)) ? vlmax_cluster : vlen_cluster_t'(acc_req_i.rs1);
+                      if ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_cluster_d)]) ||
+                          (vl_tot >= vlmax_cluster)) begin
+                        vl_d = vlmax;
+                      end else begin
+                        vl_d = vl_base;
+                        vl_d += (vl_rem >= (cluster_id_i+1) * NrLanes) ? NrLanes :
+                                (vl_rem >= (cluster_id_i * NrLanes)) ? vl_rem_diff : '0;
+                      end
+                      vl_cluster_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_cluster_d)]) ||
+                                      (vl_tot >= vlmax_cluster)) ? vlmax_cluster : vlen_cluster_t'(acc_req_i.rs1);
                     end
                   end
                 end

hardware/src/vlsu/align_stage.sv

@@ -160,7 +160,6 @@ assign axi_req_o.ar_valid = axi_req_i.ar_valid && axi_resp_o.ar_ready;
 assign axi_req_o.b_ready = axi_req_i.b_ready;
 
 assign axi_req_o.r_ready  = axi_req_cut_ready[0];
-assign axi_req_cut_ready[NumStages] = axi_req_i.r_ready;
 
 // Resp channel assignments
 assign axi_resp_o.ar_ready = axi_resp_i.ar_ready && !tracker_full; 
@@ -256,9 +255,11 @@ always_comb begin
   axi_resp_o.r_valid    = 1'b0;
   axi_resp_o.r          = axi_resp_i_cut[NumStages].r;
   axi_resp_o.r.last     = 1'b0;
+
+  axi_req_cut_ready[NumStages] = axi_req_i.r_ready;
 
   // For a valid handshake assign to buffer to be used later
-  if (axi_resp_i_cut[NumStages].r_valid && axi_req_cut_ready[NumStages]) begin
+  if (axi_resp_i_cut[NumStages].r_valid && axi_req_i.r_ready) begin
     // Buffer data in this cycle
     data_d = axi_resp_i_cut[NumStages].r.data;
     data_valid_d     = 1'b1;
@@ -269,7 +270,7 @@ always_comb begin
 
   if (!(tracker_q[rd_resp_pnt_q[NumStages-1]].op inside {VLXE, VLSE})) begin
     // Combine the previous data and the current data packets using byte enable
-    if (data_valid_q && axi_req_cut_ready[NumStages]) begin
+    if (data_valid_q && axi_req_i.r_ready) begin
       // Number of elements in a single AXI transaction
       automatic vlen_t axi_valid_el = AxiDataBytes >> tracker_q[rd_resp_pnt_q_del[NumStages-1]].vew;
 
@@ -300,9 +301,19 @@ always_comb begin
           // If the current data is not misaligned and we have a valid data
           // Set valid data for the next subsequent load to avoid bubble
           data_valid_d = be_final_d[AxiDataBytes-1] & axi_resp_i_cut[NumStages].r_valid;
+
+          // If misaligned but we already have a response for the next request,
+          // stall it for 1 cycle
+          if (!be_final_d[AxiDataBytes-1] & !axi_resp_i_cut[NumStages].r.last) begin
+            axi_req_cut_ready[NumStages] = 1'b0;
+          end
+
           last_d = 1'b0;
         end
       end
+    end else if (data_valid_q & !axi_req_i.r_ready) begin
+      // Maintain the delayed pointer in the case data cannot be sent out
+      rd_resp_pnt_d_del[NumStages-1] = rd_resp_pnt_q_del[NumStages-1];
     end
   end else begin
     // Indexed operation