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The RAK4631 overlay declares no zephcore,rtc-i2c candidate, so a fitted RAK12002 (RV3028 at 0x52) is never probed or written. The node keeps the time across a warm reboot only in noinit RAM, so any reset that loses RAM starts it on the soft clock until the next GPS, app or CLI time sync. Declare the RV3028 alone, with the descriptor rtc-i2c.dtsi uses. Not the whole of that file: its DS3231 candidate at 0x68 shares the address of WisBlock IMUs. 0x52 is clear of every address sensors-i2c.dtsi declares. A board without the module fails the probe and is skipped. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
A real RTC resets its time registers to defined values. An erased EEPROM at a candidate's address reads 0xFF everywhere, its status register too, and 0xFF has the power-loss bit set in every descriptor's mask, so the probe adopted it as a lost-power RTC and every sync wrote the time into it. 24-series EEPROMs answer within 0x50-0x57, which includes the RV3028's 0x52 that the RAK4631 now declares, so a WisBlock EEPROM module fitted without a RAK12002 could be taken for one. Skip a candidate whose seven time bytes are all 0xFF. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The RV3028 ships with backup switchover disabled (EEPROM 37h, BSM = 00), so a RAK12002 lost the time on every power cut although its supercapacitor could carry it: after removing all power the chip came back with PORF set. An optional descriptor property, rv3028-eeprom-config, lists (register, mask, value) triplets for the chip's EEPROM-backed configuration. When the chip is adopted, any register whose masked bits differ is written in RAM and committed with the EEPROM Update command, following the RV-3028-C7 Application Manual's own procedure (rev 1.4, 4.6.9: EERD = 1, edit 35h-37h, EECMD 00h then 11h, EERD = 0), as Zephyr's drivers/mfd/mfd_rv3028.c does. Committing to EEPROM matters: with EERD = 0 the chip refreshes its configuration RAM from EEPROM at power-on and every 24 hours (Control 1 register, EERD; manual p. 39), so a RAM-only setting reverts within a day. An unchanged chip costs no EEPROM write. The RAK4631 overlay sets CLKOUT off (35h CLKOE) and, in 37h, direct switching mode with the trickle charger on through 3 kOhm (TCE, BSM, TCR), leaving the factory-calibrated EEOffset bit and FEDE alone. RAK documents the RAK12002's backup as a supercapacitor, so charging it is right; the shared rtc-i2c.dtsi sets nothing, since other boards' backup supplies are not known. Fixes fork issue #33. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The comment said an RTC never reads all 0xFF. The RV3028 cannot: its time registers reset to 0 (RV-3028-C7 Application Manual, Seconds register). A chip that leaves its time undefined at first power-on could, and is then skipped for that boot only: no write-back until a later boot finds it with defined time. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… writes Review of the switchover change found the EEPROM step weaker than Zephyr's and the manual's: - The comparison was against the RAM mirror, which may hold a value no EEPROM ever got (a failed commit, or firmware that writes RAM only): the node then never commits, and the next midnight refresh reverts the setting. RAM is now refreshed from EEPROM first (EECMD 12h), as Zephyr's driver does, so the comparison is against what is stored. - After an EEPROM command it now waits 10 ms before polling EEbusy, as the manual requires (4.6.7), and every command's failure is reported. - The written registers are read back, so a password-locked chip (EEPWE set) reports "not applied" instead of "committed". - EERD was left set when the first EEbusy wait failed; it is now always cleared once it has been set. - Nothing RV3028-specific is written unless the time block's always-zero bits read 0 (Seconds b7, Minutes b7, Hours b7:6, Weekday b7:3, Date b7:6, Month b7:5; manual 3.2). Another part answering at the address, a 24-series EEPROM for one, is then left alone. - A BUILD_ASSERT requires the property to be whole triplets. Corrections to the previous commit's message: the 24-hour automatic refresh is in Control 1, EERD (manual p. 23, and 4.6.2 p. 54); the power-on refresh happens whatever EERD is (4.6.1). Direct switching is what the manual's rechargeable-backup application circuit specifies for a capacitor (7.3, p. 105: "DSM Backup Switchover Mode for capacitors (or LSM for rechargeable battery)"), although 4.2.2 cautions against DSM when VDD and VBACKUP are close. CLKOUT off saves VDD current; CLKOUT is already off on backup. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…h only The always-zero-bit check skipped only the configuration step. A chip that failed it was still adopted, and every time sync wrote seven bytes and the status byte into it: a programmed 24-series EEPROM answering at the RAK4631's 0x52 would lose data. At a descriptor that carries rv3028-eeprom-config, such a chip is now not adopted at all. rv3028-eeprom-config now acts only on 35h-37h, the EEPROM-backed configuration registers it is for; any other register is logged and ignored, so a devicetree typo cannot, say, enable password protection or rewrite EEPROM on every boot. The wait before polling EEbusy is now 1 ms after a Refresh and 10 ms after an Update, as the manual gives for reads and writes (4.6.7). Corrections to earlier messages and comments: the 3 kOhm trickle resistor is the delivery default (37h TCR = 00), not a choice section 7.3 makes; the read-back is ZephCore's, not something Zephyr's driver does; and a chip with EEPWE set is locked only while its password register does not match (4.18.1), so "password-locked" means that. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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📝 WalkthroughWalkthroughThe RTC discovery driver now accepts optional RV3028 EEPROM configuration, applies settings to the first adopted candidate, and retries incomplete configuration. Discovery skips all-0xFF time blocks and checks reserved time bits on configured RV3028 candidates. ChangesRTC discovery and RV3028 configuration
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~45 minutes Change: Bug fix Sequence Diagram(s)sequenceDiagram
participant Devicetree
participant ZephyrRTCDiscover
participant RV3028
Devicetree->>ZephyrRTCDiscover: Provide EEPROM configuration triplets
ZephyrRTCDiscover->>RV3028: Read configured EEPROM bytes
ZephyrRTCDiscover->>RV3028: Write differing masked values
ZephyrRTCDiscover->>RV3028: Refresh RAM and verify configured bits
Suggested reviewers: Merge Risk: 🔵 Low · up to If another device shares the RTC address, a failed confirmation read can cause unintended configuration writes. Reject that candidate before merging, or explicitly accept the bounded risk. Architecture SummaryArchitecture risk: 🟡 Medium · up to The change affects 1 system. Changed systems: Architecture concerns Review detailsSystems and components
Before / after behavior
Reliability and maintainability
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✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 71.43% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 14 functions across 2 files. (2 skipped: 2 unsupported.) ✨ Finishing Touches 💡 1📝 Generate docstrings 💡
🧪 Generate unit tests (beta)
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Copilot review overview
🟡 Changes recommended
Unresolved critical RTC activation and EEPROM-wear risks remain, along with documentation corrections.
Review effort: Lite
Findings: 1
Open (3)
What changed in this PR
Adds RAK12002 RV3028 RTC support for RAK4631, including persistent backup-switchover configuration and safer device discovery.
Changes:
- Adds RV3028 EEPROM configuration binding.
- Declares and configures the RTC in the RAK4631 overlay.
- Implements EEPROM refresh, update, verification, and collision guards.
| File | Summary | Findings |
|---|---|---|
zephcore/dts/bindings/rtc/zephcore,rtc-i2c.yaml |
Defines RV3028 EEPROM configuration metadata. | Moderate (2 votes): masks and duplicate triplets can cause repeated EEPROM writes. Nit (1 vote): Kconfig help omits EEPROM-write and backup-supply risks. |
zephcore/boards/nrf52840/rak4631/board.overlay |
Declares and configures the fitted RAK12002 RTC. | Nit (1 vote): Kconfig help should document EEPROM writes and backup-supply requirements. |
zephcore/adapters/clock/ZephyrRTCDiscover.c |
Implements RTC probing and EEPROM configuration. | Critical (1 vote): all-0xFF time data can permanently prevent a real RTC from becoming active. Moderate (4 votes): procedure citations are incomplete or inaccurate. |
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From Copilot's review of #35 and the last local pass: - A real RTC whose time block reads all 0xFF (some leave it undefined at power-on) was skipped and, with the probe run once at boot, never adopted for that boot: no sync was persisted. A save now probes again when a candidate was skipped that way and nothing was adopted; a real RTC's counter has moved off all 0xFF by then, an erased EEPROM has not. - A rv3028-eeprom-config triplet whose mask covers an unimplemented bit (35h bits 5:4, manual 3.15.4) or that repeats a register made every boot see a difference and run an EEPROM Update. Such triplets, like those outside 35h-37h, are now ignored with a warning, and the binding says so. - The config step's comment now cites each step's section: refresh is 4.6.4 (and Zephyr's init), the read-back is ours. - ZEPHCORE_RTC_AUTODISCOVER's help no longer says boards opt in only by including rtc-i2c.dtsi, and mentions the EEPROM configuration write. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…aution From the local pass over the review-fix push: - The read-back after an Update read the RAM mirror, which keeps what was written whether or not the EEPROM write completed, so "config committed to EEPROM" could be logged for a commit that did not land. A Refresh now follows the Update, so the read-back sees the EEPROM. Checked on a RAK4631 + RAK12002 by flashing a build with TCR = 01 and then the real one: each first boot logged "config committed to EEPROM" and restored the time. - The all-0xFF re-probe ran on every save while nothing was adopted, giving a non-RTC on a board with several descriptors a fresh chance at adoption each time. It now runs once per boot, and its comment no longer claims the counter has certainly moved. - The BUILD_ASSERT also bounds the property to what cfg_len (uint8_t) holds. - The RAK4631 overlay comment now states the manual's 4.2.2 caution against DSM with VDD and VBACKUP close, and why 7.3's DSM is kept. A residual risk remains, and the earlier message overstated it as closed: a 24-series EEPROM at 0x52 whose first seven bytes leave every always-zero bit clear and whose byte 0Eh is odd still reads as a lost-power RV3028 and is adopted. The manual specifies no fixed ID value for a stronger check. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
When restore never ran, zephcore_rtc_save() probed and then, in the same call, re-probed straight away for an all-0xFF candidate, too soon for an RTC to have counted, and used up the once-per-boot re-probe. The re-probe now runs only on a later save. The flag's comment now says the re-probe runs the whole probe, not only for the skipped candidate. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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A recorded local strict-review pass covers head |
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Answering Copilot's overview headline on 9e9452f (round): "Correct the misleading restore log during save-time RTC re-probing." Open, recorded. This is item 2 in the PR body's open list, also raised by the local review. The re-probe from |
This was referenced Oct 4, 2026
From the local pass over 9e9452f: - ZephyrRTCDiscover.h said candidates come only from rtc-i2c.dtsi and that any present chip becomes the write-back target. It now says a board overlay can declare one, which chips are adopted (never an all-0xFF block), that adopting one with rv3028-eeprom-config can write its EEPROM (about 70 ms), and that a save can run the probe once more, in the caller's context, which for ZephyrRTCClock is the system work queue. - A probe run from zephcore_rtc_save() logged "RTC ...: restored" for a time it did not restore, as the restore-never-ran path did before the re-probe existed. Only the restore path logs it now. Two earlier messages on this branch are inaccurate, and the squashed upstream commit replaces both: - 9d52ff4 understates the residual risk. A 24-series EEPROM at 0x52 whose time-block bytes leave every always-zero bit clear is adopted if those seven bytes are valid BCD, whatever 0Eh holds, and also if they are not but 0Eh bit 0 is set. Odd 0Eh is the second case only. - 778a9e3 says the RV3028's time registers reset to 0. Date and Month reset to 01h (manual 3.18). Its conclusion, that a powered RV3028 never reads all 0xFF from reset, still holds. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The 37h triplet's mask 0x2F left FEDE (bit 4) as the chip held it. FEDE is 1 on delivery and the manual's 3.15.6 says it "should always be set to 1": it lets the switchover logic follow a fast VDD edge. A chip that other firmware left with FEDE clear kept it clear. Mask 0x3F, value 0x34 now set it, which costs no EEPROM write on a chip that still has the delivery value. Raised by the MeshCore session working the same RV3028 fix there. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The RV-3028-C7 manual's 3.15.6 says BSM must be 00 or 10 "to read/write from/to the EEPROM", and 4.6.8 that a write which loses VDD is corrupted. The config step ran its Refresh on every boot, and its one Update, with direct switchover live. On the first boot it wrote BSM = 01 into RAM just before the Update. On the RAK12002 the trickle-charged supercap sits about 0.25 V under VDD, the case 4.2.2 warns can switch needlessly, and an Update rewrites all of 30h-37h, the factory trim included. The step now holds automatic refresh off, saves 37h and clears its BSM in RAM, then reads each configured byte from the EEPROM with the single-byte command (4.6.6) and writes it with the single-byte command (4.6.5) only if it differs. A closing Refresh restores RAM, and with it the stored BSM, from the EEPROM, and the written bytes are read back. If the Refresh did not complete, the saved 37h is written back so switchover is not left off. EEbusy is polled every 1 ms instead of 10 ms, and EERD is now set before EEbusy is checked, in the order 4.6.7 gives. The header no longer says adoption blocks for about 70 ms, which was wrong even before this change. Zephyr's drivers/mfd/mfd_rv3028.c and drivers/eeprom/eeprom_rv3028.c also access the EEPROM with switchover live. Tested on a RAK4631 + RAK12002, repeater debug build: - A build with 37h TCR = 01 logged "config committed to EEPROM" and restored the time; this build then committed TCR = 00 back. - A reboot logged no config line (nothing differed) and restored. - 31 s with USB unplugged (no battery fitted): restored, power-loss flag clear, so switchover was enabled again after the config step. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
From the local pass over 7b6a82a: - A config step that failed after clearing BSM restored 37h with one unchecked write, then cleared EERD. A bus fault lasting through both left backup switchover off and automatic refresh held, so not even the midnight refresh put BSM back: a power cut before the next boot lost the time, and the only log was "config not applied". What could not be put back is now kept, retried on every save, and logged as an error until it is. - The header's restore contract did not say that a chip at an RV3028 descriptor is refused when an always-zero bit reads 1, nor that adoption turns switchover off while it reads the EEPROM, and can wait up to ~66 ms more behind the chip's power-on refresh. Checked on the RAK4631 + RAK12002: flash and reboot each restored the time with no config line and no warning. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
From the local pass over 46bfd7c, which found the retry it added wrong: - The retry wrote back the 37h RAM held before the step. If the step's EEPROM write had landed, a later Refresh (the step's own, finishing after its EEbusy poll failed, or the midnight one) loaded the new 37h, and the retry then overwrote it with the old value, turning switchover off for up to a day. A save now re-runs the whole config step instead, which reads the EEPROM afresh, so it cannot restore a stale value, and holds switchover off for its EEPROM access as the first run did. - Inside the step, a Refresh that did not complete is tried once more, which restores the stored switchover mode and cannot be stale; only if that fails too is the pre-step 37h written back. - A failed retry logged nothing after boot. Each failed run now logs "config not applied, retried on the next save". - The header's save contract now says a save re-runs an incomplete config step. Saves follow GPS, app and CLI syncs, so without one the step waits for the next boot; with EERD clear, the midnight refresh restores switchover from the EEPROM in the meantime. 46bfd7c's message claimed a failure is "logged as an error until it is" put back; that was not true of the code it carried. Checked on the RAK4631 + RAK12002: flash and reboot each restored the time with no config line and no warning. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
From the local pass over e5a8d0a. The maintainer chose to simplify: - The in-step second Refresh was sent without checking EEbusy, so a chip still busy with an earlier command ignored it and the code took it as done, leaving BSM 00. It is gone. - The fallback wrote the 37h RAM held before the step, which is stale once the step's EEPROM write has landed and been refreshed into RAM; e5a8d0a's message claimed otherwise. The fallback now writes 37h with the configured bits applied, as MeshCore's fix does. It is a RAM write, so the EEPROM and 3.15.6 are not involved, and it never puts back an older value. - A step that can never complete (a password-locked RV3028, or an EEPROM impostor that passes the always-zero check) re-ran on every save. A save now re-runs it at most three times per boot. Checked on the RAK4631 + RAK12002: flash and reboot each restored the time with no config line and no warning. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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This was referenced Oct 4, 2026
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Inline comments:
Review comments at @zephcore/adapters/clock/ZephyrRTCDiscover.c:
- Around line 400-424: Update the RV3028 confirmation logic around
`rv3028_time_bits_ok` so a failed second `i2c_burst_read` skips the candidate
before it can reach `rv3028_configure`. Preserve the existing rejection when the
second read contradicts RV3028 register bits and adoption when confirmation
succeeds.
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zephcore/Kconfigzephcore/adapters/clock/ZephyrRTCDiscover.czephcore/adapters/clock/ZephyrRTCDiscover.hzephcore/dts/bindings/rtc/zephcore,rtc-i2c.yaml
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This was referenced Oct 4, 2026
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Upstream: liquidraver#98, from the clean single-commit branch |
This was referenced Oct 4, 2026
…idraver#98's rebase The owner's review of liquidraver#98 asked for a rebase onto dev dropping what liquidraver#99 provides, plus four changes. This merge carries all of them: - liquidraver#99's identify rules replace this branch's all-0xFF skip and re-probe, its hardcoded RV3028 always-zero check, and its "time unreadable" path. The RAK4631 node now carries zero-mask, as rtc-i2c.dtsi does. - The EEPROM store runs only on a clean identification (RTC_FOUND). A device adopted on a failed second read (RTC_FOUND_GARBLED) is the time write-back target but is never configured. - At an rv3028-eeprom-config descriptor the time is read once more with BSF cleared before and checked after (manual 4.2, p. 45: a switchover disables the I2C interface, so a read's tail comes back 0xFF, and a tail inside the year byte can still be valid BCD). Known limitation 1. - All RV3028 code is gated on DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY, so a board without rv3028-eeprom-config carries none of it. - The RV3028 defines no longer split the BCD2BIN/BIN2BCD pair. - The overlay comment says any other RV3028 at 0x52 gets the same settings, trickle charging included. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Local review of the liquidraver#98 rework: - A BSF set during the boot time read now also skips the EEPROM store for that boot: the EEPROM needs VDD (manual 4.6.8, p. 57), and a switchover has just shown it is not steady. - zephcore_rtc_save() at an rv3028-eeprom-config descriptor writes the time block with the same BSF bracket. A switchover mid-write keeps the bytes before the cut, a mixed time that reads as valid with PORF clear. The write is retried once, and if both fail the year register is zeroed, so the next boot reads "time not yet set" instead of restoring it. - The Kconfig help, header and binding now state the clean-identification gate, and that the RAM fallback lasts until the next refresh from EEPROM, which is daily only while EERD is clear. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Second local review round, and the same findings from the MeshCore session's mirror of the previous commit: - The zero-year fallback is gone. Its write most likely NACKs inside the switchover it targets (4.2: I2C is off in VBACKUP and for tDEB after), and when the burst write never went out it could zero a good time. An unconfirmed write is now repeated every 5 s from a delayed work item, with the time run on from the save, until one is confirmed or a newer save replaces it. MeshCore's #3421 work takes the same position: an interrupted time write is never left standing silently. - A store skipped at boot (identification failed on the second read, or BSF during the time read) is now retried from the existing 10-minute retry, and each retry identifies the chip again before any write. Two reads that rule it out stop the retries. - The bracket's comment no longer claims a cut write keeps the bytes before the cut: 5.10 says only that integrity is not guaranteed. - Kconfig help states the switchover gate and the bracketed read and write; header and binding describe the retries. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Third review round, authorized by Pieter, plus two rules agreed across the MeshCore, ZephCore and Zephyr RV3028 work: - Time write order: year 00h first, 00h-05h, then the real year, inside the BSF bracket. A write cut by a power loss, which takes the MCU down and so is never repeated, leaves year 2000: the next boot reads "time not yet set" and still adopts the chip, since identity ignores the year. Month 00h was rejected as the marker: liquidraver#99's identity rules would then rule a real RV3028 out. Writing seconds restarts the prescaler (4.5.1), so no tick lands between the writes. MeshCore #3421's work uses the same order. - EEbusy: after a Refresh that did not complete, and for the RAM-only fallback, 37h is written with switchover on only once EEbusy reads 0; otherwise switchover stays off until a retry or the daily refresh (3.15.6). Same rule as Zephyr #121252's work and MeshCore #3545's. - A store skipped at boot counts as the first try, so it gets 3 retries like a failed one, not 4. - The time-write repeat stops after 12 attempts (about a minute) and logs once, so a locked or silent chip is not written every 5 s for the rest of uptime. - The header states that zephcore_rtc_save() must run on the system work queue, which its repeat shares state with. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The RAM fallback after a failed EEPROM store was evaluated inside LOG_WRN's arguments, and Zephyr does not evaluate them when logging is off (CONFIG_LOG=n in prj.conf, so every release image). A release build whose store failed therefore never set the config in RAM, and on a chip still holding its delivery EEPROM switchover stayed off. Only debug builds ran it. Present since 334d9f7. The fallback, and its EEbusy gate, now run into a bool before the log line; the release RTC object gains the RAM write it was missing. Also from the fourth local review pass: the binding states the EEbusy condition on the RAM fallback, the header counts the save repeat as 12 repeats (13 attempts, matching the log), and the write-order comment no longer claims no tick can land between all three writes. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…r lines Comment and documentation only; the RTC object's code is byte-identical in release and debug builds. From the fourth local review pass: - A save is "confirmed" by acknowledgements and a clear BSF, not a read back, so a password-locked chip that ignores the writes passes; the comment no longer says it never confirms. - After a failed store, switchover is off only if the store had already disabled it; header and binding now say so. - The write-order comment credits the final year write, not the burst, with overwriting a tick that lands before it. - The Kconfig help names the "chip is the one adopted" condition. The header's RV3028 text is now its own paragraph after liquidraver#99's, so liquidraver#99's lines are no longer reflowed, and over-long lines are rewrapped. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Comments only; the RTC object's code is byte-identical. The review of the previous commit found five claims that overstated the code, mostly about password-locked chips and tick timing. Rather than refine them, they are removed: the write-order, save-repeat, EEbusy and retry comments now state only what the code does, and the Kconfig help puts the adoption condition on the EEPROM commit alone, not on the BSF-bracketed time read and write. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Comments only; the RTC object's code is byte-identical. The year-last order covers a power loss after the first byte and before the last; a cut inside the final one-byte year write leaves that byte undefined (5.10). The Kconfig help separates the identifying read from the BSF-checked boot time read. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Comments only; the RTC object's code is byte-identical. A cut write's outcome at the next boot depends on where the cut lands (5.10), so the comment states only that no time is taken from it. The store can follow a clean read on a retry, not only at boot, and the Kconfig help says so. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This was referenced Oct 5, 2026
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Closed unmerged: the change merged upstream as liquidraver#98 ( |
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Iteration branch for fork issues #4 and #33. Keep it open; never merge it. A clean single-commit branch for upstream is cut from it once it has baked. Upstream takes PRs on
dev.Manual references are to the RV-3028-C7 Application Manual, Rev. 1.4, November 2021 (Micro Crystal, RV-3028-C7), cited as §section and page. Code links are permalinks:
devatf9d01cf, this branch at26c5e33.The defect
Two separate failures, both on a RAK4631 with a RAK12002 fitted (an RV3028 at 0x52).
zephcore,rtc-i2ccandidate (board.overlay,dev), sortc_probe()never sees the chip. The time survives a warm reboot only in noinit RAM (ZephyrRTCClock.cpp), so every power cut starts the node at 1970 until the next GPS, app or CLI sync.The RAK12002's backup is a supercapacitor. §7.3 (p. 105) specifies direct switching (DSM) with the trickle charger for a capacitor backup, and adds: "Power Management settings have to be stored in EEPROM for permanent configuration". A RAM-only setting does not last: with EERD = 0 the chip reloads its configuration RAM from EEPROM at power-on and every day at midnight (§4.6.2, p. 54), and §4.6.9 (p. 57) warns that "the new, changed configurations are lost as soon as a refresh occurs".
The fix
board.overlay#L224-L239), with the descriptorrtc-i2c.dtsiuses for it (rtc-i2c.dtsi#L53). Only that candidate: the file's DS3231 at 0x68 (#L35) shares the address of WisBlock IMUs.rv3028-eeprom-configproperty (binding) holds (register, mask, value) triplets for the configuration registers 35h-37h. The RAK4631 sets:rv3028_store_config()stores it in EEPROM following the manual, including §3.15.6 (p. 39), which says BSM must be 00 or 10 to read or write the EEPROM:rv3028_eeprom_idle()ends the wait on the first failed status read rather than polling a dead bus through each transfer's 1000 ms timeout.rv3028_eeprom_read()/rv3028_eeprom_write()). Waits follow §4.6.7: 1 ms after a read or Refresh and 10 ms after a write before polling EEbusy.rv3028_configure()): if the config is not stored, it is set in the RAM mirror (rv3028_set_ram()), which lasts until the chip's next daily refresh. If it is stored but EERD could not be cleared, that is logged apart, since EERD = 1 also stops the daily refresh. Either way the store is retried by a delayed work item on the system work queue every 10 minutes, at most 3 times per boot (#L330-L337), and each failed attempt is logged.rtc_probe():0xFF(an erased part) is never adopted, and a later save probes once more, since a real RTC may power up that way.rv3028_time_bits_ok(), call). A failed second read does not count, so a real RV3028 on a glitchy bus is still adopted; with no clean read it becomes the write-back target but gives no time ("time unreadable"), so a block detected as garbled is never decoded.An already-configured chip costs two EEPROM byte reads and a Refresh per boot, and no EEPROM write.
Notes for review
mfd_rv3028.crun a Refresh, and a whole-block Update of 30h-37h, with switchover live. Testing on two boards found no spurious switchovers either way (Testing). The §3.15.6 sequence was chosen on the manual, jointly for this PR, the MeshCore fix (Store RV3028 backup switchover and trickle charger config in EEPROM (iteration branch) meshcore-dev-MeshCore#11) and a Zephyr driver change:rtc-i2c.dtsisets none of this, because other boards' backup supplies are not known, and trickle charging a primary cell is wrong.dev.<= 99) and hours (<= 23after masking) checks can skip a real RTC that another firmware left with an out-of-range year byte or in 12-hour mode, and only the RV3028 descriptor has an always-zero mask. MeshCore's identity work (Adopt an RTC only if its time registers read like that chip (iteration branch) meshcore-dev-MeshCore#14) grounds masks for the DS3231 and RX8130CE and drops the year and hours checks; the same for ZephCore is a separate change, not this PR.Testing
Builds at
26c5e33:rak4631repeater and companion, andthinknode_m1(which includesrtc-i2c.dtsi, with norv3028-eeprom-config). The only compiler diagnostic is the existingZephyrFsFormat.c:52deprecation warning that plaindevalso has.Hardware: a RAK4631 with a RAK12002, USB only (no battery fitted), repeater debug builds. A throwaway diagnostic patch, not on this branch, logged RAM 35h/37h, status 0Eh, Control 1 and the RTC's own time every 15 s, logged the EEPROM bytes the store read, timed the switchover-off window, and cleared BSF after each boot's first log. Before rows B and D the chip's EEPROM was restored to its delivery values (35h =
C0, 37h =10) by a build of4ce81bawith that config. ThetimeCLI command set the clock from the host just before each cut. The board also carries a RAK12501 GNSS (L76K) but sits indoors with no fix, so GPS never set the clock during these tests; behaviour with a real fix was covered by outdoor testing for the earlier upstream RTC and GNSS changes.Power cut (USB unplugged and replugged by the maintainer):
clockdevf9d01cf00:00 - 1/1/1970 UTC: time lost72bfc7b+ diagnostic, delivery EEPROM (RAM 35h/37hC0/10, BSM = 00)2000-01-01 00:00:06;present, power-loss flag set11: PORF = 1, BSF = 000:00 - 1/1/1970 UTC: time lost334d9f7+ diagnosticrestored 2026-10-04 15:09:22 UTC30: BSF = 1, PORF = 015:09 - 4/10/2026 UTC: time kept; the RTC read 0.9 s behind the host, the whole-second truncation of thetimesetRow D's image was built before a header-comment amend, so its code is
334d9f7's;26c5e33differs from it only in comments and in the garbled-read path, which needs a bus fault to reach.EEPROM store, row D's build from delivery EEPROM:
C0/1040/34config committed to EEPROM; switchover off 52.2 ms40/3440/3440/34before and after 00:00:0040/3440/34Earlier on this branch: a build with 37h TCR = 01 committed and verified, then the real config committed back, at
7b6a82aandcd5b5e3; and a 31 s cut at7b6a82akept the time.Spurious switchovers: a diagnostic build of
7b6a82a, logging 0Eh every 30 s with DSM and the trickle charger on, ran about 55 minutes across a reboot and a serial-DFU flash and recorded no BSF outside a deliberate cut. The MeshCore board, running the same §3.15.6 sequence (ptr727/meshcore-dev-MeshCore#11), recorded none over about 50 minutes.Not tested on hardware: the RAM fallback, the EERD-only failure path, the retry and the garbled-read path, which need fault injection; a battery-fitted board; temperature.
Known, left for the next iteration (from the last local passes; none is reached on a healthy chip and bus):
Refs #4, #33
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