feat: rv64 cuda hintstore by 876pol · Pull Request #2748 · openvm-org/openvm

876pol · 2026-04-23T21:17:02Z

Resolves INT-7554.

Pure rename of extensions/riscv/circuit/cuda/include/rv32im/ to extensions/riscv/circuit/cuda/include/riscv/ with matching updates to #include paths in src/*.cu. No content changes.

github-actions · 2026-04-23T21:17:16Z

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I'll analyze this and get back to you.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

github-actions · 2026-04-23T21:23:19Z

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github-actions · 2026-04-23T21:26:52Z

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shuklaayush

approved with some comments

shuklaayush · 2026-04-24T15:40:55Z

    uint32_t *__restrict__ d_range_checker,
    uint32_t range_checker_num_bins,
    uint32_t *__restrict__ d_bitwise_lookup,
    uint32_t bitwise_num_bits,


this is unrelated but can you do a cleanup in a follow-up pr to remove this argument and use a constant instead? we're passing RV64_CELL_BITS as u32 as bitwise_num_bits from rust and it doesn't make sense to use a runtime value here. also do a sweep for other kernels so we don't pass constants as arguments

github-actions · 2026-04-24T18:42:56Z

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Code Review: rv64 cuda hintstore

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This PR ports the CUDA hintstore kernel from RV32 to RV64, updating struct names, constants, and field sizes to match the Rust-side Rv64HintStore* types. I verified the CUDA struct layouts and arithmetic against the Rust AIR constraints and fill_trace_row.

Overall: Looks good. The RV32→RV64 rename is consistent and the key arithmetic matches the Rust side.

Verified correctness

REM_WORDS_NUM_LIMBS = 2 (hintstore.cu:18): Matches Rust-side const REM_WORDS_NUM_LIMBS: usize = 2 at mod.rs:57. The rem_words_limbs array correctly shrinks from 4 (RV32) to 2 limbs since rem_words fits in 10 bits.
Rv64HintStoreCols struct layout: Field types and sizes match the Rust Rv64HintStoreCols<T> at mod.rs:61-79:
- rem_words_limbs[REM_WORDS_NUM_LIMBS] → [T; REM_WORDS_NUM_LIMBS]
- mem_ptr_limbs[RV64_WORD_NUM_LIMBS] (4) → [T; RV64_WORD_NUM_LIMBS]
- data[RV64_REGISTER_NUM_LIMBS] (8) → [T; RV64_REGISTER_NUM_LIMBS]
- write_aux templated on RV64_REGISTER_NUM_LIMBS (8)
mem_ptr advancement (hintstore.cu:88): local_idx * RV64_REGISTER_NUM_LIMBS (8) matches Rust filler at mod.rs:605.
Range check arithmetic (hintstore.cu:110-121): All shift factors match the Rust AIR (mod.rs:248-252) and CPU filler (mod.rs:565-601):
- msl_rshift = (4-1) * 8 = 24 ✓
- msl_lshift = 4 * 8 - pointer_max_bits ✓
- rem_words_msl_lshift = 2 * 8 - 10 = 6 ✓
- num_words >> (8 * 1) & 0xFF correctly extracts rem_words_limbs[1] ✓
static_assert (hintstore.cu:13-16): Good upgrade from the CUDA_DEBUG-gated runtime assert to a compile-time static_assert. This is exactly what the reviewer suggested.
Data byte range checks (hintstore.cu:154-157): Loop over RV64_REGISTER_NUM_LIMBS (8) limbs in pairs, matching the Rust AIR at mod.rs:258-262.

Minor notes

Host-side asserts (hintstore.cu:219-220): I agree with shuklaayush's comment — height being a power of two and >= rows_used are invariants guaranteed by the Rust caller (next_power_of_two_or_zero at cuda.rs:64). They're cheap host-side checks though, and consistent with other kernels, so not a blocker.
bitwise_num_bits parameter (hintstore.cu:215): Per shuklaayush's comment, this is always RV64_CELL_BITS (8) and could be a constant instead of a runtime argument. Agreed that's worth a follow-up cleanup PR across all kernels.

No correctness issues found.

…uda-hintstore

github-actions · 2026-04-24T21:49:13Z

Claude finished @876pol's task in 2m 3s —— View job

Code Review: rv64 cuda hintstore

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This PR ports the CUDA hintstore kernel from RV32 to RV64 and fixes several stale references across the riscv circuit crate. I verified the CUDA struct layouts, arithmetic constants, and range-check logic against the Rust-side AIR constraints and fill_trace_row.

Overall: Looks good. The RV32→RV64 rename is consistent, constants are correct, and the key arithmetic matches the Rust side.

Verified correctness

REM_WORDS_NUM_LIMBS = 2 (hintstore.cu:18) — Matches Rust const REM_WORDS_NUM_LIMBS: usize = 2 at mod.rs:57. The rem_words_limbs array correctly shrinks from 4 (RV32) to 2 since rem_words fits in 10 bits (MAX_HINT_BUFFER_DWORDS_BITS).
Rv64HintStoreCols struct layout — Field types and sizes match the Rust Rv64HintStoreCols<T> at mod.rs:61-85:
- rem_words_limbs[2] → [T; REM_WORDS_NUM_LIMBS] ✓
- mem_ptr_limbs[4] → [T; RV64_WORD_NUM_LIMBS] ✓
- data[8] → [T; RV64_REGISTER_NUM_LIMBS] ✓
- write_aux templated on RV64_REGISTER_NUM_LIMBS (8) ✓
mem_ptr advancement (hintstore.cu:88) — local_idx * RV64_REGISTER_NUM_LIMBS (8) matches Rust filler at mod.rs:593,646. ✓
Range check arithmetic (hintstore.cu:110-121) — All shift factors match the Rust AIR (mod.rs:223-241) and CPU filler (mod.rs:547-589):
- msl_rshift = (4-1) * 8 = 24 ✓
- msl_lshift = 4 * 8 - pointer_max_bits ✓
- rem_words_msl_lshift = 2 * 8 - 10 = 6 ✓
- num_words >> (8 * 1) & 0xFF correctly extracts rem_words_limbs[1] ✓
static_assert (hintstore.cu:13-16) — Good upgrade from CUDA_DEBUG-gated runtime assert to a compile-time static_assert. Clean improvement.
Data byte range checks (hintstore.cu:155) — Loop over RV64_REGISTER_NUM_LIMBS (8) limbs in pairs, matching the Rust AIR at mod.rs:246-249. ✓
rem_words_limbs encoding — CUDA uses reinterpret_cast<uint8_t*>(&rem_words) taking the low 2 bytes of a uint32_t. Rust filler casts to u16 then to_le_bytes(). Both yield the same 2 little-endian bytes on CUDA's little-endian architecture. ✓
cuda.rs changes — RV32_CELL_BITS → RV64_CELL_BITS in BitwiseOperationLookupChipGPU type and the tracegen call. Both are 8 but this keeps types semantically correct. ✓
Test changes (tests.rs) — All type references updated (Rv32 → Rv64), HINT_STOREW → HINT_STORED, Rv32HintStoreLayout → Rv64HintStoreLayout. Consistent with the rename. ✓

Style nit

#[cfg(all(feature = "cuda"))] and #[cfg(all(test))] in base_alu_w, divrem_w, mul_w, shift_w — cfg(all(X)) is semantically identical to cfg(X) when there's only one predicate. The rest of the codebase uses the simpler #[cfg(feature = "cuda")] and #[cfg(test)] forms. This is purely cosmetic and doesn't affect compilation, but it's inconsistent with the convention in sibling modules (branch_lt, branch_eq, shift, mul, etc.). Consider reverting to the simpler form. Fix this →

Notes on existing review comments

Host-side asserts (hintstore.cu:219-220): Agree with shuklaayush that these are guaranteed by the Rust caller (next_power_of_two_or_zero at cuda.rs:64). They're cheap host-side checks though, and other kernels have them, so this is a stylistic call.
bitwise_num_bits parameter (hintstore.cu:215): Agree this is always RV64_CELL_BITS (8) and should be a constant. Good candidate for a follow-up cleanup PR.

No correctness issues found.

github-actions · 2026-04-24T21:51:08Z

Claude finished @876pol's task in 1m 30s —— View job

Code Review: rv64 cuda hintstore

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This PR ports the CUDA hintstore kernel from RV32 to RV64, updating struct names, constants, and field sizes to match the Rust-side Rv64HintStore* types. I cross-referenced the CUDA struct layouts, arithmetic, and range-check logic against the Rust AIR constraints and fill_trace_row.

Overall: Looks correct. The RV32→RV64 rename is consistent and the key arithmetic matches the Rust side. No correctness issues found.

Verified correctness

REM_WORDS_NUM_LIMBS = 2 (hintstore.cu:18): Matches Rust const REM_WORDS_NUM_LIMBS: usize = 2 at mod.rs:57. Correct because rem_words fits in 2^MAX_HINT_BUFFER_DWORDS_BITS = 2^10 which requires only 2 bytes.
Rv64HintStoreCols struct layout (hintstore.cu:20-41): Field-by-field match with Rust Rv64HintStoreCols<T> at mod.rs:61-84:
- rem_words_limbs[REM_WORDS_NUM_LIMBS] (2) ← was 4 in RV32 ✓
- mem_ptr_limbs[RV64_WORD_NUM_LIMBS] (4) ✓
- data[RV64_REGISTER_NUM_LIMBS] (8) ← was 4 in RV32 ✓
- write_aux templated on RV64_REGISTER_NUM_LIMBS (8) ✓
mem_ptr advancement (hintstore.cu:88): local_idx * RV64_REGISTER_NUM_LIMBS (8 bytes per dword) matches the Rust filler at mod.rs:646 (mem_ptr -= RV64_REGISTER_NUM_LIMBS as u32).
Overflow guard (hintstore.cu:104): MAX_HINT_BUFFER_DWORDS_BITS + 3 < pointer_max_bits is correct — 8 * MAX_HINT_BUFFER_DWORDS needs 10 + 3 = 13 bits (was +2 for RV32's 4-byte words). ✓
Range check arithmetic (hintstore.cu:110-121): All shift factors match the Rust AIR (mod.rs:236-241) and CPU filler (mod.rs:553-558):
- msl_rshift = (4-1) * 8 = 24 ✓
- msl_lshift = 4 * 8 - pointer_max_bits ✓
- rem_words_msl_lshift = 2 * 8 - 10 = 6 ✓
- num_words >> (8 * 1) & 0xFF correctly extracts rem_words_limbs[1] ✓
static_assert (hintstore.cu:12-16): Good upgrade from CUDA_DEBUG-gated runtime assert to compile-time static_assert. This addresses shuklaayush's suggestion.
rem_words_limbs writing (hintstore.cu:89,94): CUDA writes the first 2 bytes of a little-endian uint32_t via reinterpret_cast<uint8_t *>, equivalent to the Rust filler's (rem_words as u16).to_le_bytes() at mod.rs:653. ✓
Data byte range checks (hintstore.cu:155-157): Loop over RV64_REGISTER_NUM_LIMBS (8) limbs in pairs, matching the Rust AIR at mod.rs:246-249. ✓
Test updates (tests.rs): All type references correctly updated to RV64 variants. HINT_STOREW → HINT_STORED reflects the opcode rename. ✓
Disabled test modules (load_sign_extend/mod.rs, loadstore/mod.rs): Using #[cfg(all(test, any()))] with a TODO comment is a reasonable way to disable tests pending the RV64 port.

Minor notes (non-blocking)

Host-side asserts (hintstore.cu:219-220): Per shuklaayush's comment, height being a power of two and >= rows_used are invariants guaranteed by next_power_of_two_or_zero on the Rust side (cuda.rs:64). They're cheap host-side assertions and consistent with other kernels, so fine to keep for defensive coding.
bitwise_num_bits parameter (hintstore.cu:215): Agree with shuklaayush that this is always RV64_CELL_BITS and could be a constant. Good candidate for a follow-up cleanup PR across all kernels.
cuda.rs comment sync: The comment at constants.h:94 ("Must match MAX_HINT_BUFFER_DWORDS_BITS in openvm_riscv_guest::lib.rs") is correctly updated. The corresponding Rust-side comment at guest/src/lib.rs:30 ("Must be synced with MAX_HINT_BUFFER_DWORDS_BITS constant for cuda") is also updated. ✓

No correctness issues found. LGTM.

github-actions · 2026-04-24T21:54:12Z

Claude finished @876pol's task in 1m 46s —— View job

Code Review: rv64 cuda hintstore

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This PR ports the CUDA hintstore kernel from RV32 to RV64, updating struct names, constants, and field sizes to match the Rust-side Rv64HintStore* types. I cross-referenced the CUDA struct layouts, arithmetic, and range-check logic against the Rust AIR constraints and fill_trace_row.

Overall: Looks correct. No issues found.

Verified correctness

REM_WORDS_NUM_LIMBS = 2 (hintstore.cu:18): Matches Rust const REM_WORDS_NUM_LIMBS: usize = 2 at mod.rs:57. Correct because rem_words fits in 2^MAX_HINT_BUFFER_DWORDS_BITS = 2^10, requiring only 2 bytes.
Rv64HintStoreCols struct layout (hintstore.cu:20-41): Field-by-field match with Rust Rv64HintStoreCols<T> at mod.rs:61-85:
- rem_words_limbs[REM_WORDS_NUM_LIMBS] (2) ✓
- mem_ptr_limbs[RV64_WORD_NUM_LIMBS] (4) ✓
- data[RV64_REGISTER_NUM_LIMBS] (8) ✓
- write_aux templated on RV64_REGISTER_NUM_LIMBS (8) ✓
Record structs: Rv64HintStoreRecordHeader and Rv64HintStoreVars (hintstore.cu:44-63) match Rust-side Rv64HintStoreRecordHeader (mod.rs:306-319) and Rv64HintStoreVar (mod.rs:324-327) field-by-field. ✓
mem_ptr advancement (hintstore.cu:88): local_idx * RV64_REGISTER_NUM_LIMBS (8 bytes per dword) matches the Rust filler at mod.rs:646. ✓
Overflow guard (hintstore.cu:104): MAX_HINT_BUFFER_DWORDS_BITS + 3 < pointer_max_bits is correct — 8 * MAX_HINT_BUFFER_DWORDS needs 10 + 3 = 13 bits (was +2 for RV32's 4-byte words). ✓
Range check arithmetic (hintstore.cu:110-121): All shift factors match the Rust AIR (mod.rs:234-243) and CPU filler (mod.rs:553-558):
- msl_rshift = (4-1) * 8 = 24 ✓
- msl_lshift = 4 * 8 - pointer_max_bits ✓
- rem_words_msl_lshift = 2 * 8 - 10 = 6 ✓
- num_words >> (8 * 1) & 0xFF correctly extracts rem_words_limbs[1] ✓
static_assert (hintstore.cu:12-16): Good upgrade from CUDA_DEBUG-gated runtime assert to compile-time static_assert, addressing reviewer feedback. ✓
rem_words_limbs encoding (hintstore.cu:89,94): CUDA writes the first 2 bytes of a little-endian uint32_t via reinterpret_cast<uint8_t *>. Rust filler casts to u16 then to_le_bytes() (mod.rs:653). Both yield the same 2 little-endian bytes. ✓
Data byte range checks (hintstore.cu:155): Loop over RV64_REGISTER_NUM_LIMBS (8) limbs in pairs, matching the Rust AIR at mod.rs:246-249. ✓
cuda.rs changes: RV32_CELL_BITS → RV64_CELL_BITS in BitwiseOperationLookupChipGPU type and the tracegen call. Both constants are 8, but this keeps types semantically correct for the RV64 context. ✓
Test updates (tests.rs): All type references correctly updated to RV64 variants. HINT_STOREW → HINT_STORED reflects the opcode rename. ✓
constants.h rename: MAX_HINT_BUFFER_WORDS_BITS → MAX_HINT_BUFFER_DWORDS_BITS and MAX_HINT_BUFFER_WORDS → MAX_HINT_BUFFER_DWORDS. Comment updated to match. ✓
Guest lib comment (lib.rs:29): Updated to reference MAX_HINT_BUFFER_DWORDS_BITS. ✓

Notes on existing review comments

Host-side asserts (hintstore.cu:219-220): Agree with shuklaayush that height being a power of two and >= rows_used are guaranteed by next_power_of_two_or_zero on the Rust side (cuda.rs:64). They're cheap host-side checks and consistent with other kernels, so fine either way.
bitwise_num_bits parameter (hintstore.cu:215): Agree this is always RV64_CELL_BITS (8) and could be a constant. Good candidate for a follow-up cleanup PR.

LGTM — no correctness issues found.

github-actions · 2026-04-24T21:56:55Z

Claude finished @876pol's task in 1m 31s —— View job

Code Review: rv64 cuda hintstore

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This PR ports the CUDA hintstore kernel from RV32 to RV64, updating struct names, constants, and field sizes to match the Rust-side Rv64HintStore* types. I cross-referenced the CUDA struct layouts, arithmetic, and range-check logic against the Rust AIR constraints (mod.rs:216-249) and fill_trace_row (mod.rs:553-658).

Overall: Looks correct. No issues found.

Verified correctness

REM_WORDS_NUM_LIMBS = 2 (hintstore.cu:18): Matches Rust const REM_WORDS_NUM_LIMBS: usize = 2 at mod.rs:57. Correct because rem_words fits in 2^MAX_HINT_BUFFER_DWORDS_BITS = 2^10, requiring only 2 bytes.
Rv64HintStoreCols struct layout (hintstore.cu:20-41): Field-by-field match with Rust Rv64HintStoreCols<T> at mod.rs:61-85:
- rem_words_limbs[2] ← was 4 in RV32 ✓
- mem_ptr_limbs[RV64_WORD_NUM_LIMBS] (4) ✓
- data[RV64_REGISTER_NUM_LIMBS] (8) ← was 4 in RV32 ✓
- write_aux templated on RV64_REGISTER_NUM_LIMBS (8) ✓
Record structs (hintstore.cu:44-63): Rv64HintStoreRecordHeader and Rv64HintStoreVars match the Rust-side Rv64HintStoreRecordHeader (mod.rs:306-319) and Rv64HintStoreVar (mod.rs:322-327) in field order and types. Field name difference (write_aux vs data_write_aux) is irrelevant since both are #[repr(C)] and layout is determined by order. ✓
mem_ptr advancement (hintstore.cu:88): local_idx * RV64_REGISTER_NUM_LIMBS (8 bytes per dword) matches the Rust filler at mod.rs:646 (mem_ptr -= RV64_REGISTER_NUM_LIMBS as u32). ✓
Overflow guard (hintstore.cu:104): MAX_HINT_BUFFER_DWORDS_BITS + 3 < pointer_max_bits is correct — 8 * MAX_HINT_BUFFER_DWORDS needs 10 + 3 = 13 bits (was +2 for RV32's 4-byte words). ✓
Range check arithmetic (hintstore.cu:110-121): All shift factors match the Rust AIR (mod.rs:234-242) and CPU filler (mod.rs:553-558):
- msl_rshift = (4-1) * 8 = 24 ✓
- msl_lshift = 4 * 8 - pointer_max_bits ✓
- rem_words_msl_lshift = 2 * 8 - 10 = 6 ✓
- num_words >> (8 * 1) & 0xFF correctly extracts rem_words_limbs[1] ✓
static_assert (hintstore.cu:12-16): Good upgrade from CUDA_DEBUG-gated runtime assert to compile-time static_assert, addressing shuklaayush's suggestion. ✓
rem_words_limbs encoding (hintstore.cu:89,94): CUDA writes the first 2 bytes of a little-endian uint32_t via reinterpret_cast<uint8_t *>. Rust filler casts to u16 then to_le_bytes() (mod.rs:653). Both yield the same 2 little-endian bytes on CUDA's little-endian architecture. ✓
Data byte range checks (hintstore.cu:155): Loop over RV64_REGISTER_NUM_LIMBS (8) limbs in pairs, matching the Rust AIR at mod.rs:246-249. ✓
cuda.rs changes: RV32_CELL_BITS → RV64_CELL_BITS in BitwiseOperationLookupChipGPU type and the tracegen call. Both constants equal 8, but this keeps types semantically correct for the RV64 context. ✓
Test updates (tests.rs): All type references correctly updated. HINT_STOREW → HINT_STORED reflects the opcode rename. Tests are now re-enabled (#[cfg(test)] replaces #[cfg(all(test, any()))]). ✓
constants.h (constants.h:93-97): MAX_HINT_BUFFER_WORDS_BITS → MAX_HINT_BUFFER_DWORDS_BITS with matching comment update. ✓
cfg(all(...)) cleanup: The previous review noted cfg(all(feature = "cuda")) / cfg(all(test)) in sibling modules — I confirmed this has already been cleaned up; no instances remain.

Notes on existing review comments

Host-side asserts (hintstore.cu:219-220): Per shuklaayush's comment, height being a power of two and ≥ rows_used are invariants guaranteed by next_power_of_two_or_zero on the Rust side (cuda.rs:64). They're cheap host-side checks and consistent with other kernels, so fine to keep.
bitwise_num_bits parameter (hintstore.cu:215): Agree this is always RV64_CELL_BITS (8) and could be a constant. Good candidate for a follow-up cleanup PR across all kernels.

LGTM — no correctness issues found.

876pol and others added 15 commits April 22, 2026 18:22

rv64 system airs

15cd0a7

style: cleanup

b2916bc

fix: revert inventory.cu

88cc615

feat: changes

e1ee024

Merge branch 'develop-v2.1.0-rv64' into rv64-cuda-system-airs

1b960a4

feat: changes

8a2be9f

feat: revert changes

6bec494

style: comments

a930850

style: comments

97e92c0

refactor: rename cuda include directory rv32im to riscv

b8f4470

Pure rename of extensions/riscv/circuit/cuda/include/rv32im/ to extensions/riscv/circuit/cuda/include/riscv/ with matching updates to #include paths in src/*.cu. No content changes.

feat: rv64 cuda easy instructions

037333d

style: cleanup

67f4609

style: update stale names

d021e78

rv64 cuda hintstore

1e85cba

style: asserts

f9cc8ae

style: fix stale doc reference to MAX_HINT_BUFFER_DWORDS_BITS

d256d1a

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

876pol requested review from shuklaayush April 23, 2026 21:26

876pol marked this pull request as ready for review April 23, 2026 21:26

shuklaayush approved these changes Apr 24, 2026

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fix: restore assert

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876pol force-pushed the rv64-cuda-easy-instructions branch from ff9047b to e24c55e Compare April 24, 2026 20:37

876pol force-pushed the rv64-cuda-easy-instructions branch from e24c55e to ff9047b Compare April 24, 2026 20:43

Base automatically changed from rv64-cuda-easy-instructions to develop-v2.1.0-rv64 April 24, 2026 20:53

876pol added 2 commits April 24, 2026 21:43

Merge remote-tracking branch 'origin/develop-v2.1.0-rv64' into rv64-c…

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…uda-hintstore

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feat: rv64 cuda hintstore#2748

feat: rv64 cuda hintstore#2748
876pol wants to merge 24 commits intodevelop-v2.1.0-rv64from
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