USB3 support for A733

arch/arm64/boot/dts/allwinner/sun60i-a733-demo-aiot.dts

@@ -187,6 +187,13 @@
 	status = "okay";
 };
 
+&pcie_rc {
+	reset-gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+	wake-gpios = <&pio 8 13 GPIO_ACTIVE_HIGH>;
+	pcie3v3-supply = <&swout2>;
+	status = "okay";
+};
+
 &pio {
 	/* PF = SD, PB = UART0, PG = Wi-Fi (DCDC1 3.3V) */
 	vcc-pf-supply = <&swout2>;
@@ -407,6 +414,13 @@
 	cpu-supply = <&reg_dcdc3>;
 };
 
+&serdes {
+	serdes1v8-supply = <&cldo5>;
+	avdd-c-supply = <&reg_dcdc2>;
+	avdd-d-supply = <&reg_dcdc2>;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins>;

arch/arm64/boot/dts/allwinner/sun60i-a733.dtsi

@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/sun60i-a733-rtc.h>
 #include <dt-bindings/clock/sun60i-a733-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/allwinner,sun60i-a733-pck-600.h>
 #include <dt-bindings/reset/sun60i-a733-ccu.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/reset/sun60i-a733-r-ccu.h>
@@ -774,6 +775,145 @@
 			};
 		};
 
+		pcie_rc: pcie@6000000 {
+			compatible = "allwinner,sunxi-pcie-v300-rc";
+			bus-range = <0x0 0xff>;
+			reg = <0 0x06000000 0 0x480000>;
+			reg-names = "dbi";
+			device_type = "pci";
+			clocks =  <&ccu CLK_PCIE0_AUX>,
+				  <&ccu CLK_PCIE0_AXI_SLV>,
+				  <&ccu CLK_ITS_PCIE0_A>;
+			clock-names = "pclk_aux", "pclk_slv", "its";
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "sii", "msi", "edma-w0", "edma-w1", "edma-w2", "edma-w3",
+					  "edma-r0", "edma-r1", "edma-r2", "edma-r3";
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc 0>,
+					<0 0 0 2 &pcie_intc 1>,
+					<0 0 0 3 &pcie_intc 2>,
+					<0 0 0 4 &pcie_intc 3>;
+			linux,pci-domain = <0>;
+			max-link-speed = <3>;
+			num-edma = <4>;
+			num-lanes = <1>;
+			num-ib-windows = <16>;
+			num-ob-windows = <16>;
+			phys = <&combo1_pcie>;
+			phy-names = "pcie-phy";
+			power-domains = <&pck600 PD_PCIE>;
+			ranges = <0x00000800 0 0x20000000 0x0 0x20000000 0 0x01000000
+				  0x81000000 0 0x21000000 0x0 0x21000000 0 0x01000000
+				  0x82000000 0 0x22000000 0x0 0x22000000 0 0x06000000>;
+			resets = <&ccu RST_BUS_PCIE0>,
+				 <&ccu RST_BUS_PCIE0_PWRUP>,
+				 <&ccu RST_BUS_ITS_PCIE0>;
+			reset-names = "pclk_rst", "pwrup_rst", "its";
+			#address-cells = <3>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			pcie_intc: legacy-interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		serdes: serdes@6c00000 {
+			compatible = "allwinner,cadence-combophy";
+			reg = <0x0 0x06c00000 0x0 0x400>,
+			      <0x0 0x06c06000 0x0 0x2000>,
+			      <0x0 0x0709016c 0x0 0x4>;
+			clocks = <&ccu CLK_SERDES_PHY_CFG>,
+				 <&rtc_ccu CLK_RTC_DCXO_SERDES0>,
+				 <&rtc_ccu CLK_RTC_DCXO_SERDES1>;
+			clock-names = "serdes-clk",
+				      "dcxo-serdes0-clk",
+				      "dcxo-serdes1-clk";
+			ranges;
+			resets = <&ccu RST_BUS_SERDES>;
+			reset-names = "serdes-reset";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			combophy0: combo-phy0@6c01000 {
+				reg = <0x0 0x06c01000 0x0 0xa00>,
+				      <0x0 0x06c80000 0x0 0x20000>;
+
+				combo0_dp: combo0-dp-phy {
+					#phy-cells = <0>;
+					status = "okay";
+				};
+
+				combo0_usb: combo0-usb-phy {
+					#phy-cells = <0>;
+					status = "okay";
+				};
+			};
+
+			combophy1: combo-phy1@6c02000 {
+				reg = <0x0 0x06c02000 0x0 0xa00>,
+				      <0x0 0x06ca0000 0x0 0x20000>;
+
+				combo1_usb: combo1-usb-phy {
+					#phy-cells = <0>;
+					status = "okay";
+				};
+
+				combo1_pcie: combo1-pcie-phy {
+					#phy-cells = <0>;
+					status = "okay";
+				};
+			};
+
+			aux_hpd: aux-hpd@6c01e00 {
+				reg = <0x0 0x06c01e00 0x0 0x200>;
+
+				aux_hpd_phy: aux-hpd-phy {
+					#phy-cells = <0>;
+					status = "okay";
+				};
+			};
+		};
+
+		xhci: usb@6a00000 {
+			compatible = "allwinner,sun60i-a733-dwc3";
+			reg = <0x0 0x6a00000 0x0 0x100000>;
+			dr_mode = "otg";
+			clocks = <&ccu CLK_USB2_MF>, <&ccu CLK_USB2_U2_REF>,
+				 <&ccu CLK_USB2_SUSPEND>,
+				 <&ccu CLK_USB2_U3_UTMI>, <&ccu CLK_USB2_U2_PIPE>;
+			clock-names = "bus_clk", "ref_clk", "suspend",
+				      "utmi", "pipe";
+			resets = <&ccu RST_USB_2>;
+			assigned-clocks = <&ccu CLK_USB2_SUSPEND>, <&ccu CLK_USB2_MF>;
+			assigned-clock-rates = <24000000>, <300000000>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			maximum-speed = "super-speed-plus";
+			phy_type = "utmi";
+			power-domains = <&pck600 PD_USB2>;
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			phys = <&usbphy 2>, <&combo1_usb>;
+			phy-names = "usb2-phy", "usb3-phy";
+			status = "disabled";
+		};
+
 		r_ccu: r_ccu@7010000 {
 			compatible = "allwinner,sun60iw2-r-ccu";
 			reg = <0x0 0x07010000 0x0 0x340>;

drivers/pci/controller/Kconfig

@@ -358,6 +358,7 @@ config PCIE_XILINX_CPM
 	  Say 'Y' here if you want kernel support for the
 	  Xilinx Versal CPM host bridge.
 
+source "drivers/pci/controller/allwinner/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"

drivers/pci/controller/Makefile

@@ -41,6 +41,7 @@ obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
 obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
 
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
+obj-y				+= allwinner/
 obj-y				+= dwc/
 obj-y				+= mobiveil/
 obj-y				+= plda/

drivers/pci/controller/allwinner/Kconfig

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2015-2025 Allwinner Technology Co., Ltd.
+
+menu "Allwinner PCIe Drivers"
+	depends on PCI
+
+choice
+	prompt "Allwinner PCIe controller support"
+	default PCIE_SUNXI_NONE
+
+config PCIE_SUNXI_RC
+	bool "RC controller - Host mode"
+	help
+	  Enables support for the PCIe RC controller in the Allwinner SoC.
+
+config PCIE_SUNXI_EP
+	bool "EP controller - Endpoint mode"
+	select PCI_ENDPOINT
+	help
+	  Enables support for the PCIe EP controller in the Allwinner SoC.
+
+config PCIE_SUNXI_NONE
+	bool "None"
+	help
+	  Disable support for the PCIe controller in the Allwinner SoC.
+
+endchoice
+
+endmenu

drivers/pci/controller/allwinner/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2015-2025 Allwinner Technology Co., Ltd.
+pcie_sunxi_host-objs := pcie-sunxi-rc.o pcie-sunxi-dma.o pcie-sunxi-plat.o
+pcie_sunxi_ep-objs := pcie-sunxi-ep.o pcie-sunxi-dma.o pcie-sunxi-plat.o
+obj-$(CONFIG_PCIE_SUNXI_RC) += pcie_sunxi_host.o
+obj-$(CONFIG_PCIE_SUNXI_EP) += pcie_sunxi_ep.o