VLSI Engineering Student passionate about RTL Design, Digital Verification, Embedded Systems, and IoT. Currently building open-source Verilog hardware projects.
- BENGALURU
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07:58
(UTC -05:00) - https://www.linkedin.com/in/nithin-n-j-6955bb379/
Popular repositories Loading
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vlsi-smart-irrigation-system
vlsi-smart-irrigation-system PublicVLSI-oriented Smart Irrigation Controller featuring Verilog RTL modules, self-checking testbenches, FSM-based control, and planned ESP32 IoT integration.
Verilog
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calculator-asic
calculator-asic PublicAn industry-style ASIC Calculator project demonstrating the complete RTL-to-GDSII design flow using Verilog, Yosys, OpenROAD, Magic, and FPGA prototyping.
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aes128-fault-detection
aes128-fault-detection PublicVerilog simulation of AES-128 encryption with S-box and round-output parity fault detection.
Verilog
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