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[Deprecated] RISC-V IEEE 754 Floating point Support - #449

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NLS-04 wants to merge 43 commits into
mortbopet:masterfrom
NLS-04:floating-point-extension-system
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[Deprecated] RISC-V IEEE 754 Floating point Support#449
NLS-04 wants to merge 43 commits into
mortbopet:masterfrom
NLS-04:floating-point-extension-system

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@NLS-04 NLS-04 commented Apr 27, 2026

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This PR depends on the PR #448

Summary

This PR introduces a new extension management system in Ripes, replacing the previous string-literal based handling with a typed abstraction interface.
It is built on top of the floating-point integration work and prepares the codebase for cleaner extension composition, dependency handling, and future ISA growth.

The implementation is modular and keeps compatibility with existing processor models while migrating them to the new interface.


This PR is part of the same staged effort:

  1. PR [Deprecated] RISC-V IEEE 754 Floating point Support #448 : core floating-point integration and processor groundwork
  2. PR [Deprecated] RISC-V IEEE 754 Floating point Support #449 (This one): extension management system overhaul and architecture integration
  3. PR RISC-V IEEE 754 Floating point Support #450 : processor registration/selection refactor

In this Pull-Request

Impact

  • Replaces brittle extension string handling with a typed and extendable abstraction
  • Improves correctness and maintainability of extension enable/disable logic
  • Enables explicit extension dependencies (implicated extensions) and canonical ordering
  • Creates a robust base for upcoming extension work and non-RISC-V extension models
  • Simplifies integration points for processors, CLI, and ISA construction

What Changed

Core Extension System

  • Added polymorphic extension interfaces for:
    • extension identity and comparison
    • user-facing metadata
    • compiler march naming
    • extension implication relationships
  • Added generic extension-set interface:
    • canonical container behavior
    • recursive extension search
    • subset/equality operations
    • cloning and mutation helpers
  • Added ISA registry logic that caches/returns ISA objects by enabled extension set

RISC-V Integration

  • Added a dedicated RISC-V extension manager with canonical extension definitions
  • Reworked RISC-V ISA base setup to:
    • validate selected extension sets
    • load extension instructions via extension-provided enable hooks
    • generate march strings from extension set contents
  • Updated RV32/RV64 ISA constructors and initialization to use extension-set driven setup
  • Updated decode/uncompress and processor-side handling to use the new extension type interface

MIPS Integration (just for integrity)

  • Adapted MIPS ISA wiring to the new extension-set abstractions

CLI and Runtime Integration

  • Updated CLI extension argument validation against the new extension container/search interface
  • Updated model startup path to enable selected extensions through the typed system

+ changed registerfile interface so that the register count can be set
+ changed registerfile interface so that the zero register can be hardwired to zero or be regular register
+ change is backwards compatible with existing integrations
made expression parser object orientated to be more versatile for implementations like float, double etc. and added floating point parsing and computation.
the currently handling of extension of all default (ss, 5s, 6s)  processors advertised all extension the RVIsa is capable of, but since adding floating point support to a processor requires a separate processors design/class this default advertising must be restricted to just the extensions the specific processor supports.
required to test floating point tests
@NLS-04
NLS-04 marked this pull request as ready for review April 27, 2026 11:34
@NLS-04
NLS-04 marked this pull request as draft May 13, 2026 00:00
@NLS-04 NLS-04 changed the title [2/3] RISC-V IEEE 754 Floating point Support [Deprecated] RISC-V IEEE 754 Floating point Support May 16, 2026
@NLS-04 NLS-04 closed this May 22, 2026
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