[Deprecated] RISC-V IEEE 754 Floating point Support - #449
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+ changed registerfile interface so that the register count can be set + changed registerfile interface so that the zero register can be hardwired to zero or be regular register + change is backwards compatible with existing integrations
made expression parser object orientated to be more versatile for implementations like float, double etc. and added floating point parsing and computation.
…mode and csr register constants
the currently handling of extension of all default (ss, 5s, 6s) processors advertised all extension the RVIsa is capable of, but since adding floating point support to a processor requires a separate processors design/class this default advertising must be restricted to just the extensions the specific processor supports.
…ot the architecture bitwidth
required to test floating point tests
…to be easier to test
This was referenced Apr 27, 2026
NLS-04
marked this pull request as ready for review
April 27, 2026 11:34
NLS-04
marked this pull request as draft
May 13, 2026 00:00
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This PR depends on the PR #448
Summary
This PR introduces a new extension management system in Ripes, replacing the previous string-literal based handling with a typed abstraction interface.
It is built on top of the floating-point integration work and prepares the codebase for cleaner extension composition, dependency handling, and future ISA growth.
The implementation is modular and keeps compatibility with existing processor models while migrating them to the new interface.
This PR is part of the same staged effort:
In this Pull-Request
Impact
What Changed
Core Extension System
RISC-V Integration
MIPS Integration (just for integrity)
CLI and Runtime Integration