Emit hierarchical annotations for Verilator

[teqdruid]

Some of our Verilator compilations are quite long. Like 15 to 20 minutes. One way to speed it up is with hierarchical verilation: https://veripool.org/guide/latest/verilating.html#hierarchical-verilation

It might be a good idea to attach a /*verilator hier_block*/ to each exported class.

[matthew-humphrey]

Check out the list of limitations in the Verilator doc page you linked. This one in particular is concerning:

Generated clocks may not work correctly if generated in the hierarchical model and passed into another hierarchical model or the top module.

[teqdruid]

The way ESI cosim works is we have a C++ driver app which drives the clock so this limitation certainly doesn't apply.

Also, by "hierarchical model" I assume the documentation is referring to doesn't include the "top level" compilation unit. So if one is passing the clock into the top level Kanagawa module (and not generating it from inside Kanagawa, which isn't possible) I also don't think this limitation applies.