This project is based on SNESTang by nand2mario. The IcePi-Zero variant is nicknamed SNESPi and provides in-FPGA USB 2.0 HID support using the usb_hid_host core.
For a MiSTle-compatible build, follow the build guide in MiSTle-Dev/snescore.
On IcePi-Zero boards, USB 2.0 HID support runs entirely in FPGA gateware through usb_hid_host, supporting low-speed and full-speed devices. See the IcePi-Zero Minimig USB support notes for details about device compatibility and limitations.
On IcePi-Zero, the first player uses the second USB port, the one closer to the PCB edge, for easier physical access. The other USB port is for the second player.
MiSTle GW5A-25 devboard and IcePi-Zero support the GSU (Super FX) chip thanks to the cache implementation. All GSU games work except DOOM, which hangs randomly. The suspected cause is its need for predictable memory-access timing; this has not been confirmed.
Star Fox and Super Mario World 2: Yoshi's Island both work—two standout titles that make GSU support worthwhile on their own.
IcePi-Zero XL uses BRAM-backed memory for GSU instead of the cache-backed SDRAM path. DOOM is expected to work there with the more predictable memory timing.
Controllers without dedicated Start and Select buttons can use these chords:
| Hold | Press | SNES button |
|---|---|---|
| X + Y | A | Start |
| X + Y | B | Select |
The mapping applies to both players and all controller inputs. Dedicated Start and Select buttons still work. While either chord is held, its face buttons are not sent to the game; directions and shoulder buttons still work.
Press Select + Right to open the on-screen display (OSD).
At a high level, the work since fbd8217 includes:
- Changed the I/O soft CPU to SERV in its 4-bit QERV mode to reduce FPGA resource use. The I/O system was also refactored and gained streamed ROM loading.
- Updated the SNES core modules from the upstream MiSTer SNES core, keeping the migrated VHDL sources where practical. The 65C816 CPU uses its Verilog implementation because the VHDL version used too many LUTs.
- Migrated all of nand2mario's improvements, including the existing SNESTang integration and features.
- Added MiSTle board support and adapted the build, memory, HDMI, and audio paths for Gowin and Lattice ECP5 targets. Simulation was restored for the mixed Verilog/VHDL design.
- Added an IcePi-Zero project and connected the USB HID host to its USB ports.
First, get firmware.bin from the forked SNESTang firmware repository and flash it at offset 0x500000:
openFPGALoader -b icepi-zero --write-flash --offset 0x500000 firmware.binThen flash the IcePi-Zero core bitstream:
openFPGALoader -b icepi-zero --write-flash path/to/core.bitReplace path/to/core.bit with the path to the built bitstream. Flash the firmware before using the core.
The design notes describe the original SNESTang architecture. The Verilator harness provides simulation support.
SNESTang was created by nand2mario as part of TangCore. Its SNES core derives from SNES_FPGA by Sergiy Dvodnenko (srg320) and gyurco and the MiSTer SNES core. HDMI support uses hdl-util/hdmi by Sameer Puri.