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Pull requests: lnis-uofu/OpenFPGA
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Added -x option to the openfpgashell executable
openfpga-tools
VPR
#2442
opened Apr 3, 2026 by
ganeshgore
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Fix wire-LUT annotation for fractured LUT outputs after repack
openfpga-tools
#2439
opened Apr 2, 2026 by
amin1377
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Add windows macos builds
build
github
lang-make
openfpga-tools
VPR
#2437
opened Apr 1, 2026 by
coolbreeze413
•
Draft
[WIP] Strong testcase for Single-Stage Routing
architecture-description
tests
#2425
opened Mar 23, 2026 by
tangxifan
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4 of 18 tasks
[WIP] Remapping Bitstream
architecture-description
documentation
flow-scripts
openfpga-bitstream
openfpga-tools
tests
#2414
opened Mar 6, 2026 by
ganeshgore
•
Draft
Bump yosys from Pull requests that update a dependency file
submodules
Pull requests that update Submodules code
407d425 to 679156d
dependencies
#2392
opened Feb 20, 2026 by
dependabot
bot
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[fabric_bitstream] Adding custom bitstream remap
openfpga-bitstream
openfpga-tools
#2022
opened Jun 4, 2025 by
amin1377
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Use hierarchical block names
openfpga-tools
VPR
wontfix
This will not be worked on
#1976
opened Apr 7, 2025 by
amin1377
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Make sure net is valid before setting it as wire LUT output
openfpga-tools
#1719
opened Jun 19, 2024 by
chungshien
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Preserve escaped names
openfpga-tools
openfpga-verilog
#1589
opened Mar 4, 2024 by
alaindargelas
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Relative paths in run_modelsim.py and other changes to make Modelsim work on non-Utah machines
architecture-description
flow-scripts
#247
opened Feb 20, 2021 by
nachiket
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3 of 16 tasks
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