feat: build the aarch64 and riscv64 kernel (cross-arch skeleton) - #138
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The generic kernel referenced x86-only arch submodules directly
(crate::arch::x86_64::{clone,init,sched_glue,...}, oncrix_hal::arch::
x86_64::uart), so only x86_64 built. Introduce an arch-neutral facade:
kernel and hal arch/mod.rs re-export the active target's submodules
under crate::arch::* / oncrix_hal::arch::* per #[cfg(target_arch)], and
generic callers use those neutral paths. Provide aarch64 and riscv64
arch submodules (clone, context, init, init_embed, sched_glue,
syscall_entry) with signature-matching build stubs, plus aarch64 (PL011)
and riscv64 (NS16550) uart shims exposing COM1/Uart16550. x86_64 is
unchanged. Non-x86 runtime bodies are honest stubs (unimplemented!/no-op)
pending real context-switch/clone support; this lands a compiling
cross-arch skeleton.
cachefiles::CacheBackend inlined [Option<CacheVolume>; 32] where each CacheVolume is ~134 MiB, making the struct ~4.3 GiB by value. Building it in CacheBackend::default() needs a >2 GiB stack frame, which the riscv64 backend rejects (signed-32-bit frame-offset limit), aborting codegen. Box the volume slots ([Option<Box<CacheVolume>>; 32]) so the struct is pointer-sized and volumes are heap-allocated lazily; capacity, behaviour, and the private API are unchanged.
Legacy x86 device drivers (PS/2, VGA text, RTL8139/ATA/AC97/SB16 PIO, PC speaker, CMOS, 8250/16550 port-I/O, uhci, e100, ne2k, ...) issued in/out and other x86 port-I/O instructions unconditionally, failing to build on aarch64/riscv64 (invalid register dx/ax/al). Gate the x86 asm behind #[cfg(target_arch = "x86_64")] with type-correct non-x86 fallbacks (default read / no-op write) so the crate builds on all three targets; x86 behaviour is unchanged.
A newer nightly clippy flags the tree-wide 'for slot in &mut self.table
{ *slot = None; }' clear pattern (fixed-capacity inline tables) as
manual_slice_fill. .fill(None) is not always applicable (non-Copy
elements) and the loop is clear, so allow it workspace-wide, matching the
existing large_const_arrays allow. Unblocks workspace clippy CI.
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Completes the cross-arch kernel build:
cargo build -p oncrix-kernelnow succeeds on x86_64, aarch64, and riscv64 (previously only x86_64). oncrix-drivers also builds on all three.What was blocking
crate::arch::x86_64::{clone,init,sched_glue,...},oncrix_hal::arch::x86_64::uart); the aarch64/riscv64 submodules didn't exist → 24 unresolved-path errors.cachefiles::CacheBackendwas ~4.3 GiB by value ([Option;32], each ~134 MiB) → riscv64 codegen aborted with a >2 GiB stack-frame LLVM error.in/outport-I/O asm unconditionally → aarch64/riscv64invalid registererrors.Changes
arch/mod.rsre-exports the active target's submodules undercrate::arch::*/oncrix_hal::arch::*per#[cfg(target_arch)]; generic callers use the neutral paths. New aarch64 + riscv64 arch submodules (clone/context/init/init_embed/sched_glue/syscall_entry) with signature-matching build stubs; aarch64 (PL011) + riscv64 (NS16550) uart shims exposing COM1/Uart16550. x86_64 unchanged.#[cfg(target_arch="x86_64")]with type-correct non-x86 fallbacks.Scope note
Non-x86 runtime bodies are honest stubs (
unimplemented!/no-op) pending real context-switch/clone/trap support — this lands a compiling cross-arch skeleton, not a bootable aarch64/riscv64 kernel yet.Verified
cargo build -p oncrix-kernelon x86_64/aarch64/riscv64 = 0 errors;cargo build --workspace(x86) = 0;cargo fmt --all --check+cargo clippy --workspace -- -D warnings= clean. No x86 regression.