# 5-Stage Pipelined RISC Processor

The design focuses on:

A 5-stage pipelined RISC processor with forwarding, hazard detection, and branch prediction support.
P3 lays out the skeleton of the processor.
P4 makes the processor to be pipelined.
P5 adds the hazard detection unit.
P6 adds the forwarding units.
P7 adds multicycle cache memory.

## Project Architecture

### High-Level Design

```text
+-------------------+
| Instruction Fetch |
+-------------------+
          |
          v
+-------------------+
| Instruction Decode|
+-------------------+
          |
          v
+-------------------+
| Execute Stage     |
+-------------------+
          |
          v
+-------------------+
| Memory Stage      |
+-------------------+
          |
          v
+-------------------+
| Writeback Stage   |
+-------------------+

Main Components

• ALU

  • Arithmetic and logical operations

• Register File

  • Dual-read single-write architecture

• Control Unit

  • Generates datapath control signals

• Pipeline Registers

  • IF/ID, ID/EX, EX/MEM, MEM/WB

• Hazard Detection Unit

  • Handles stalls and data hazards

• Forwarding Unit

  • Reduces pipeline stalls

---

Features

• 5-stage pipelined architecture
• Data forwarding
• Hazard detection
• Branch handling
• Parameterized modules
• Testbench support
• Cache implementation
• Branch predictor

---

Getting Started

Prerequisites

Install:

• Icarus Verilog / ModelSim / QuestaSim
• GTKWave
• Make

Example (Ubuntu):

sudo apt install iverilog gtkwave make

---

Running Simulation

Compile

make compile

Run Tests

make test

Open Waveforms

gtkwave waveform/output.vcd

---

Example Test Output

[PASS] ALU addition test
[PASS] Register file write/read
[PASS] Pipeline forwarding
[PASS] Branch instruction test

Verification Strategy

The design was verified using:

• Directed testbenches
• Randomized testing
• Waveform inspection
• Corner-case validation

Key verified scenarios:

• RAW hazards
• Load-use hazards
• Branch flush behavior
• Memory operations