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simulation: cleanup and reuse of Yocto DTB/DTSs. - #25
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juanschroeder
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Sep 7, 2026
juanschroeder
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- align CV32A6S+ FPGA CPU clock frequency with CV32A6
- print full verilator command
- rework of usage and modification of device trees. New script added and no DTS from this repo is used.
- Fixed simulation targets (and QEMU) which were not working with latest Yocto deploy artifacts changes.
- align CV32A6S+ FPGA CPU clock frequency with CV32A6 - print full verilator command - rework of usage and modification of device trees. New script added and no DTS from this repo is used. - Fixed simulation targets (and QEMU) which were not working with latest Yocto deploy artifacts changes. Signed-off-by: Juan Schroeder <jcschroeder@gmail.com>
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