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Cvwsoc rework more - #24
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Fixes: - Update SDHC module and add parameter for a timing improvement. It's not clear in the end if this helped, so it is currently disabled for Genesys 2. - Other timing config was improved/changed. CVA6S+ changes: - updated Pulp CVA6 to v3.0 - updated dependencies: fpnew (cvfpu), hpdcache - removed redundant dependency (fpnew duplicated cvfpu). - Using official CVA6S+ (RV64) config plus small overrides - Created new CVA6S+ RV32 config. There is no official CVA6S+ RV32 config upstream, so this is kind of a test - Simulation also supports CVA6SP=1 (including RV32=1) - Remark: no D extension for CV32A6, so no Linux FPU support Other changes: - CVA6 now uses hpdcache by default. This improved performance and affected based CVA6 config, so that had to be retested. - zicbom extension is supported in this version with hpdcache - Added new cvwsoc CVA6SP CPU config and Wally config parameters - created new builds for CVA6S+ for Genesys 2 and Nexys A7 - cleanup on CPU mapping - cvwsoc_axi: reworked bus infrastructure parameters so that bus setup can be flexible to meet timing constraints - updated some clock frequencies after tests - CVA6 RV32 previously used config became deprecated. Status: - Simulation tested without issues for CV*A6 configs - Tested in the FPGA. CV32A6 builds have some random stack traces that need to be investigated Signed-off-by: Juan Schroeder <jcschroeder@gmail.com>
Signed-off-by: Juan Schroeder <jcschroeder@gmail.com>
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CVA6 update, CVA6S+ integration and some further rework (see commits details).
Tested in simulation and FPGA.