Name		Name	Last commit message	Last commit date
bin		bin
docs		docs
dv/testbench		dv/testbench
regs		regs
rtl		rtl
.gitignore		.gitignore
README.md		README.md
compile.sh		compile.sh
regr.list		regr.list

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dv1

Práctica 2. Asignatura "Test y Verificación", máster semiconductores UV

https://www.edaplayground.com/x/rnnX

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