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Own selected Cortex-M cores and retain partial outcomes. - #82
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Callers that acquire several targets currently have to track which acquisitions succeeded and which targets still need restoration. Own those targets over borrowed memory, retain per-member results, and restore independent members after failure. Keep lower owners live while restoration remains pending.
Independent targets require callers to track partial stop and resume progress. Report selected outcomes in membership order, preserve unowned halts, and retain uncertain members for cleanup without replaying writes. Observe execution separately from a retained halt-request claim.
A group cannot lend raw targets without bypassing its lifecycle. Route register and step operations through its selected member and retain the same transfer, event, and cleanup rules. Exercise the composition on the prepared RP2350 counters without changing inherited CTI routing.
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@codex review Please review the individual commits as well as the final diff. The previous commit-size finding counted the complete PR as one commit; the published series already separates acquisition/release (89ecdf0, 168 added non-test Go lines), selected control (0098318, 156), and member access (4331bf6, 43), each with tests and documentation. The head remains 4331bf6. |
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Codex Review: Didn't find any major issues. You're on a roll. Reviewed commit: ℹ️ About Codex in GitHubYour team has set up Codex to review pull requests in this repo. Reviews are triggered when you
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cortexm.AcquireGroupacquires an explicit set of Cortex-M0/M33 targets over borrowed memory clients. Selected halt, resume, and status calls return per-core outcomes, including members not reached after a failure; register and step access stays inside the owned targets.The memory clients above are borrowed from one Arm owner;
r4Valueis an intentional register change which persists after release. If release fails, retain the group and Arm owner for another cleanup attempt.Group.Resultscopies the latest member outcomes without traffic.Why
Separate targets already control the RP2350 cores, but their caller must track partial progress and cleanup independently. The group owns that lifecycle, preserves inherited halts, releases only halt requests it still owns, and attempts independent cleanup after a member fails. The caller still serializes calls over the shared connection. Sequential stopping does not promise simultaneous halt, and the group does not own CTI routing.
Documentation
Update the Cortex-M guide, architecture, composition, and capability table with group ownership, selected control, member access, and cleanup limits.
Hardware evidence
On the prepared RP2350 Secure dual-counter bench, J-Link EDU Mini V2
000802011345at 1 MHz with APs0x2000/0x4000, run:Two fresh sessions read all 19 registers on each core, verified one PC/R0/RAM step per core while its peer advanced, stopped both cores sequentially, verified another core-0 step while its peer stayed stopped, and resumed only core 0. In each session, group release restored progress on both cores and their initial disabled-debug/running state before the shared owner closed; DSCSR and inactive CTI configuration were unchanged. Group release and owner close succeeded in both sessions. Post-close state was not independently measured. Register writes and injected failures were not exercised physically, and the prepared RAM programs and instruction effects remain.