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Verify Cortex-M simulator control and observation guards. - #132
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The register model had no independent checks for several documented permission, sticky-status and address rules. Invalid-address cases used invalid widths, so they could pass even if high addresses aliased. Exercise otherwise valid word accesses, selective reason clearing and read-to-clear status. Check rejected control changes before effects and verify that warm reset refreshes permission latched while halted. Keep the existing model and reset-fixture behavior unchanged.
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Codex Review: Didn't find any major issues. 👍 Reviewed commit: ℹ️ About Codex in GitHubYour team has set up Codex to review pull requests in this repo. Reviews are triggered when you
If Codex has suggestions, it will comment; otherwise it will react with 👍. Codex can also answer questions or update the PR. Try commenting "@codex address that feedback". |
The Cortex-M register model now has focused tests for disabling debug while halted, denied external halt, interrupt-mask changes while running or resuming, M33 restart read-clear status, selective DFSR clearing, invalid word addresses and warm-reset permission refresh. The tests exercise the existing model without changing its behavior.
Why
The old invalid-address rows also used invalid access widths, so they could pass even if a high address aliased a valid register. Several documented permission and observation rules likewise had no test that distinguished their removal.
The new cases use valid word buffers at invalid addresses, keep independent sticky bits set, and check snapshots before and after rejected requests. A rejected mask change must also leave a pending resume at its original completion tick. Warm-reset coverage retains the existing fixture contract.
Documentation
The constructor, register methods, event declarations and Cortex-M simulation guide already describe these rules. Their scope and behavior remain unchanged; these tests add no instruction execution or physical validation claim.