Dice cgra core integration - #7
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…other files for some reason
…to vortex cache now
…rbitration. Got slighly confused about write addressing, need to sort out where to do adress translation(bank select) for write addresses
… 'pop, can't figure out interfaces still, need to talk to jiayi probably about port connections
… to output data through the tcu though
…with Jiayi later to fix up on macro issues
…the moment, running into out of bound warnings
block commit updated / ldst takes 32 bits now
…n to fix connection
…vortex4dice into dice_cgra_core_integration
De developement aadithya
…vortex4dice into dice_cgra_core_integration
…ntiation of the memory/cache into tb, will wire tmcu later in main file
Scoreboard refactor fixed. back-to-back cta dispatch possible
…vortex4dice into dice_cgra_core_integration
Albert/backend
…ing rd_tid. Bus conected, but not the same value?
… logic and connective tissue while keeping IP. Most things wont work, just initial restructure
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