In Progress: Refactoring dispatcher to modular design. - #3
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…other files for some reason
…to vortex cache now
…rbitration. Got slighly confused about write addressing, need to sort out where to do adress translation(bank select) for write addresses
… 'pop, can't figure out interfaces still, need to talk to jiayi probably about port connections
… to output data through the tcu though
…with Jiayi later to fix up on macro issues
…the moment, running into out of bound warnings
De developement aadithya merged to main DE branch for dispatcher integration.
De developement
…dispatch test added to tb
Albert/backend
… the signals in the core still since i made some changes to some of the modules and not sure if i have correctly updated the core. Block retire table also still needs to be modified (active low reset rn)
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Initial PR request for dispatcher refactor. PR opened for me to ask questions and receive guidance as the refactor is ongoing progress.
Files in dispatcher_refactor/
In progress
Working on a redesign of the dispatcher module, making the FSM more modular for easier debugging.
Still undergoing changes and testing.
Other comments
Had a question what the dispatched_this_cycle (~line 209/210 of dispatcher.sv) does. It is currently not connected to anything or being used.
cta_total_size(~declared line 52, assigned a value line 68) is a signal that is assigned a value based on latched_cta_size however is never used.