Albert/backend - #1
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jiayi-wang98
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Thanks for the effort! Please see inline comments for changes. And for next PR, make sure that when you run the testbench, there's no warning when compiling RTLs and all testcases pass.
patrickh567
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Please address issues mentioned in comments before merging
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December 1, 2025 16:45
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Thanks for the PR. Please see inline comments of BITMAP_WIDTH.
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Looks great with some minor issues.
Please try to test in testbench with different parameters (such as 64/32-bit address width and 64/32-bit data width and other parameters) so that we can tell if we missed any place to be changed from the VCS warning "connection width mismatch".
…rbitration. Got slighly confused about write addressing, need to sort out where to do adress translation(bank select) for write addresses
block commit updated / ldst takes 32 bits now
…n to fix connection
…vortex4dice into dice_cgra_core_integration
De developement aadithya
…vortex4dice into dice_cgra_core_integration
…ntiation of the memory/cache into tb, will wire tmcu later in main file
Scoreboard refactor fixed. back-to-back cta dispatch possible
…vortex4dice into dice_cgra_core_integration
Albert/backend
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Parameterized the logic within the ldst unit files and testbenches. Test bench ran back with all test passing with original parameters, have not tried new parameters yet.