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Fix/libfabric plugin experiment - #13
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…MEM shim Add Level Zero (Intel Xe) device memory support to the libfabric plugin and nixlbench, moving GPU-vendor-specific code into separate utility files (nfi_hmem, libfabric_accel). Squashed from four commits: - Update libfabric plugin to support Intel GPUs; refactor GPU vendor specific code into separate utility files. - Update .gitignore to include install-v2/. - Fix libfabric test failures: handshake reply after a peer reconnects, default plugin directory missing in the build tree. - Fix issues found in code review: handshakes deferred off the progress thread, accelerator bind checks, unclaimed-VRAM fallback, rail pairing, CUDA primary-context caching, nixlbench Level Zero device lookup. Rebased onto main, integrating the upstream libfabric changes: - AMD GPUs: an FI_HMEM_ROCR vendor in the HMEM shim (dlopen'd HIP runtime) replaces the hipify build step, so every vendor goes through one mechanism. AMD GPUs are detected through hwloc and take part in NIC grouping. - CUDA dmabuf export per NIC: kept, keyed on the shim's iface and CUDA ordinal. - Senders identified by source address: kept. disconnect() now unmaps the peer's source addresses, so a reconnect maps afresh instead of re-mapping. - The shim's CUDA vendor is keyed on NIXL_HAVE_CUDA_DRIVER_API, not HAVE_CUDA, which ROCm builds also define. RDMA writes over verbs;ofi_rxm need a libfabric whose rxm reports the source address of remote-write completions (rxm_handle_remote_write() passed FI_ADDR_NOTAVAIL); without it the receiver cannot attribute writes. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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What?
This draft PR refactors the NIXL libfabric plugin to support Intel (Xe) GPUs. Note - this is a draft PR and will be used to do initial performance testing.
Why?
Support is needed for a new GPU vendor.
How?