Hardware: AMD Ryzen AI Max+ 395 (gfx1151, Radeon 8060S), 128 GB UMA, Mesa RADV STRIX_HALO.
Model: Qwen3.8 Flash Next qwen4exp A3B, Q4_0_ROCMFP4_FAST flat GGUF (~93 GB), DKQ=256, GQA 24q/2kv.
Backends compared: --device Vulkan0 only (ROCm excluded on the old pin - it has no HIP backend).
Env both arms: GGML_CUDA_DISABLE_GRAPHS=1 (CUDA knob; inert for Vulkan, kept constant), -ngl 99.
Repro (llama-bench, repetitions 2, stddevs <= 0.84 t/s)
llama-bench -m <flat.gguf> -p 512 -n 32 -d 0,16384,49152 \
-b 2048 -ub 512 -ngl 99 -fa on|off -r 2 --device Vulkan0 -o csv
Results (tg32 t/s per warm-KV depth)
| tree |
commit |
FA |
@0 |
@16k |
@48k |
| old fork pin |
5621d2b5c |
on |
27.18 |
24.56 |
22.72 |
| strix master |
0a37251f4 |
on |
27.81 |
23.84 |
17.67 |
| old fork pin |
5621d2b5c |
off |
26.77 |
20.05 |
8.58 |
| strix master |
0a37251f4 |
off |
28.62 |
19.60 |
7.72 |
Delta (master vs old pin): FA on: +2.3% / -2.9% / -22.2% at 0/16K/48K.
FA off: +6.9% / -2.2% / -10.0%.
Reading
- Depth-only regression: parity (or better) at depth 0, ~-3% at 16K, -22% at 48K with FA on.
- With FA off both trees collapse (non-FA KV reads at 48K are slow everywhere - expected), but
the master-vs-pin gap shrinks from -5.05 t/s to -0.86 t/s absolute at 48K.
- => ~83% of the loss is attention-path-specific at depth; a ~17% residual sits in the non-FA
decode path (KV cache layout / rope / fattn_vec fallback changes upstream between the pins).
- Same model file both arms (flat GGUF), so this is not a ple16/split-PLE artifact; the old pin
loads the flat file fine and lands within 3.5% of its own ple16 numbers (22.72 vs 23.54 tg@48K).
Context / asks
- Observed while gating a HIP cutover for this model: server-side decode ladders reproduce it
(new-tree Vulkan0 arm 16.97 t/s at ~48K ctx vs old production binary 22.37; identical probe
suite, all correctness needles clean on both).
- The CUDA/HIP side of master is separately not our suspect here: on ROCm, -fa off is WORSE than
-fa on (5.66 vs 11.72 t/s w48), i.e. the FA kernels help there; this issue is Vulkan-specific.
- CI does not cover this class (no Vulkan depth ladder). Bisect candidates between ~2026-09-05
and master HEAD: upstream fattn/fattn_vec churn, KV cache layout changes (kv-unified era),
RDNA pipeline-selection changes in ggml-vulkan. Happy to re-run any candidate build on the
Strix Halo with this exact ladder.
Evidence files (share): r29-bench-newtree-{vulkan}-, r30-bench-oldflat-vk-, r31-bench--faoff- CSVs;
server ladders r28/r29 verdicts. Happy to provide raw CSVs on request.
Hardware: AMD Ryzen AI Max+ 395 (gfx1151, Radeon 8060S), 128 GB UMA, Mesa RADV STRIX_HALO.
Model: Qwen3.8 Flash Next qwen4exp A3B, Q4_0_ROCMFP4_FAST flat GGUF (~93 GB), DKQ=256, GQA 24q/2kv.
Backends compared:
--device Vulkan0only (ROCm excluded on the old pin - it has no HIP backend).Env both arms: GGML_CUDA_DISABLE_GRAPHS=1 (CUDA knob; inert for Vulkan, kept constant), -ngl 99.
Repro (llama-bench, repetitions 2, stddevs <= 0.84 t/s)
Results (tg32 t/s per warm-KV depth)
Delta (master vs old pin): FA on: +2.3% / -2.9% / -22.2% at 0/16K/48K.
FA off: +6.9% / -2.2% / -10.0%.
Reading
the master-vs-pin gap shrinks from -5.05 t/s to -0.86 t/s absolute at 48K.
decode path (KV cache layout / rope / fattn_vec fallback changes upstream between the pins).
loads the flat file fine and lands within 3.5% of its own ple16 numbers (22.72 vs 23.54 tg@48K).
Context / asks
(new-tree Vulkan0 arm 16.97 t/s at ~48K ctx vs old production binary 22.37; identical probe
suite, all correctness needles clean on both).
-fa on (5.66 vs 11.72 t/s w48), i.e. the FA kernels help there; this issue is Vulkan-specific.
and master HEAD: upstream fattn/fattn_vec churn, KV cache layout changes (kv-unified era),
RDNA pipeline-selection changes in ggml-vulkan. Happy to re-run any candidate build on the
Strix Halo with this exact ladder.
Evidence files (share): r29-bench-newtree-{vulkan}-, r30-bench-oldflat-vk-, r31-bench--faoff- CSVs;
server ladders r28/r29 verdicts. Happy to provide raw CSVs on request.