RISCV-SingleCycle-Processor

32-bit single-cycle RISC-V processor implementation in Verilog with RV32I instruction support and FPGA validation.

32-bit Single-Cycle RISC-V Processor

Implementation of a 32-bit single-cycle RISC-V processor using Verilog HDL and simulated in Vivado.

🚀 Overview

This project implements a subset of the RV32I RISC-V instruction set architecture using a single-cycle datapath design.

The processor supports:

• Arithmetic operations
• Logical operations
• Memory access instructions
• Branch instructions
• Jump instructions
• Stack operations
• Function calls and returns

Each instruction completes in a single clock cycle.

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🧠 Architecture

The processor follows a single-cycle datapath architecture where instruction fetch, decode, execute, memory access, and write-back occur within one clock cycle.

Main Modules

• Program Counter (PC)
• Instruction Memory
• Control Unit
• Register File
• Immediate Generator
• ALU
• ALU Control
• Data Memory
• Branch Logic
• Write-back Multiplexer

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⚙️ Supported RV32I Instructions

Arithmetic & Logical

• ADD
• SUB
• ADDI
• AND
• OR
• XOR
• SLT
• SLL
• SRL

Memory Operations

• LW
• SW

Control Flow

• BEQ
• JAL
• JALR

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🧩 Processor Workflow

1. Program Counter fetches instruction address
2. Instruction Memory provides instruction
3. Instruction Decoder extracts opcode and fields
4. Control Unit generates control signals
5. Register File reads operands
6. ALU performs arithmetic or logical operation
7. Data Memory handles load/store instructions
8. Write-back logic updates registers
9. PC logic determines next instruction flow

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🧪 Verification & Testing

The processor was validated using multiple levels of testing.

✅ Level 1 — Arithmetic + Memory Validation

Tested:

• ADDI
• ADD
• LW
• SW

Verified:

• Register updates
• ALU output
• Memory read/write operations

✅ Level 2 — Branch + ALU Validation

Tested:

• Multiple ALU operations
• Branch instructions
• Comparison logic

Verified:

• Branch handling
• ALU control logic
• Instruction execution flow

✅ Level 3 — Control Flow + Stack Validation

Tested:

• JAL
• JALR
• Stack push/pop
• Nested loops
• Function calls

Verified:

• PC redirection
• Stack operations
• Function return logic

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📊 Waveform Analysis

Waveform simulations were analyzed in Vivado to verify:

• Program Counter updates
• Instruction execution
• ALU results
• Branch behavior
• Write-back operations
• Memory access signals

Important signals monitored include:

• pc
• instruction
• alu_result
• branch_taken
• write_back_data
• mem_read_data

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💡 Key Design Concepts

Single-Cycle Architecture

Every instruction completes in one clock cycle, simplifying datapath and control logic design.

Two-Level Decoding

• Control Unit performs opcode decoding
• ALU Control determines exact ALU operation using funct3 and funct7

Word-Aligned Instruction Memory

Instruction memory is indexed using:

mem[addr[31:2]]

since RISC-V instructions are 32-bit aligned.

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🛠️ Tools Used

• Verilog HDL
• Vivado
• Spartan-7 FPGA

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📚 Learning Resources & References

This project was developed through self-learning, FPGA experimentation, waveform debugging, technical documentation, and AI-assisted development workflows.

Helpful references used during development include:

• RealDigital FPGA Documentation
  https://www.realdigital.org/doc/02013cd17602c8af749f00561f88ae21

• Digilent FPGA Tutorials
  https://digilent.com/reference/learn/programmable-logic/start

Additional support tools:

• ChatGPT
• GitHub Copilot
• Vivado Simulation & Waveform Analysis

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📌 Notes

• Register x0 is hardwired to zero as defined in the RISC-V ISA.
• The processor uses a single-cycle datapath architecture.
• Stack operations use register x2 as the stack pointer.

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🔥 Future Improvements

• Pipelined architecture
• Hazard detection
• Data forwarding
• Cache memory
• UART debugging
• FPGA hardware deployment

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👨‍💻 Authors

Gilbert Franco C
Jefin Jaison Jefin jans George Sleeba ECE Student | FPGA & Embedded Systems Enthusiast