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Merged
felixtensor merged 1 commit into from
Sep 15, 2026
Merged

chore(examples): sync upstream TableGen examples to 2026-09-16 #26

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1,225 changes: 549 additions & 676 deletions examples/llvm/IR/Intrinsics.td
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44 changes: 22 additions & 22 deletions examples/llvm/IR/IntrinsicsX86.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2575,18 +2575,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_bmi_bzhi_64 : ClangBuiltin<"__builtin_ia32_bzhi_di">,
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>;
def int_x86_bmi_pdep_32 : ClangBuiltin<"__builtin_ia32_pdep_si">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_x86_bmi_pdep_64 : ClangBuiltin<"__builtin_ia32_pdep_di">,
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>;
def int_x86_bmi_pext_32 : ClangBuiltin<"__builtin_ia32_pext_si">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_x86_bmi_pext_64 : ClangBuiltin<"__builtin_ia32_pext_di">,
DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -5664,16 +5652,6 @@ let TargetPrefix = "x86" in {
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_i32_ty],
[]>;

def int_x86_tmmultf32ps : ClangBuiltin<"__builtin_ia32_tmmultf32ps">,
Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty],
[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
ImmArg<ArgIndex<2>>]>;
def int_x86_tmmultf32ps_internal :
ClangBuiltin<"__builtin_ia32_tmmultf32ps_internal">,
Intrinsic<[llvm_x86amx_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
llvm_x86amx_ty, llvm_x86amx_ty], []>;

def int_x86_tdpbf8ps_internal :
ClangBuiltin<"__builtin_ia32_tdpbf8ps_internal">,
Intrinsic<[llvm_x86amx_ty],
Expand Down Expand Up @@ -7341,4 +7319,26 @@ def int_x86_movrsdi : ClangBuiltin<"__builtin_ia32_movrsdi">,
[IntrReadMem]>;
def int_x86_prefetchrs : ClangBuiltin<"__builtin_ia32_prefetchrs">,
Intrinsic<[], [llvm_ptr_ty], []>;

//===----------------------------------------------------------------------===//
// BMM intrinsics

def int_x86_avx512_vbmacor_v16hi :
ClangBuiltin<"__builtin_ia32_bmacor16x16x16_v16hi">,
DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty],
[IntrNoMem]>;
def int_x86_avx512_vbmacor_v32hi :
ClangBuiltin<"__builtin_ia32_bmacor16x16x16_v32hi">,
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty],
[IntrNoMem]>;

def int_x86_avx512_vbmacxor_v16hi :
ClangBuiltin<"__builtin_ia32_bmacxor16x16x16_v16hi">,
DefaultAttrsIntrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty],
[IntrNoMem]>;
def int_x86_avx512_vbmacxor_v32hi :
ClangBuiltin<"__builtin_ia32_bmacxor16x16x16_v32hi">,
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty, llvm_v32i16_ty],
[IntrNoMem]>;
}
//===----------------------------------------------------------------------===//
18 changes: 14 additions & 4 deletions examples/llvm/Target/AArch64/AArch64.td
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,13 @@ def AArch64InstrInfo : InstrInfo;

include "AArch64SystemOperands.td"

//===----------------------------------------------------------------------===//
// LFI rewriter metadata consumed by AArch64MCLFIRewriter. Must follow
// AArch64SystemOperands.td due to use of SearchableTable.td.
//===----------------------------------------------------------------------===//

include "AArch64LFI.td"

//===----------------------------------------------------------------------===//
// AArch64 Processors supported.
//
Expand All @@ -60,14 +67,14 @@ include "AArch64SystemOperands.td"

class AArch64Unsupported { list<Predicate> F; }

let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
let F = [HasSVE2p1, HasSVE2p1_or_SME, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
def SVE2p1Unsupported : AArch64Unsupported;

def SVE2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
HasSSVE_FP8DOT2, HasSSVE_FP8DOT4,
HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVESM4, HasSVEBitPerm,
HasSVEB16B16],
HasSVEB16B16, HasSVEBFSCALE],
SVE2p1Unsupported.F);
}

Expand Down Expand Up @@ -98,12 +105,13 @@ def SME2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSME2, HasNonStreamingSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
HasSSVE_FP8DOT2, HasSSVE_FP8DOT4,
HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
HasNonStreamingSVE_or_SSVE_AES, HasSVE2p1_or_StreamingSME2],
HasNonStreamingSVE_or_SSVE_AES, HasSVE2p1_or_StreamingSME2, HasSME2andIsNonStreamingSafe],
SME2p1Unsupported.F);
}

def SMEUnsupported : AArch64Unsupported {
let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64],
let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64,
HasSMEandIsNonStreamingSafe],
SME2Unsupported.F);
}

Expand All @@ -119,6 +127,7 @@ include "AArch64SchedA53.td"
include "AArch64SchedA55.td"
include "AArch64SchedA510.td"
include "AArch64SchedA57.td"
include "AArch64SchedC1Nano.td"
include "AArch64SchedC1Ultra.td"
include "AArch64SchedC1Premium.td"
include "AArch64SchedCyclone.td"
Expand All @@ -132,6 +141,7 @@ include "AArch64SchedThunderX2T99.td"
include "AArch64SchedA64FX.td"
include "AArch64SchedThunderX3T110.td"
include "AArch64SchedTSV110.td"
include "AArch64SchedHIP12.td"
include "AArch64SchedAmpere1.td"
include "AArch64SchedAmpere1B.td"
include "AArch64SchedNeoverseN1.td"
Expand Down
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