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Add PerfSpect 3.x and Zen5 metric name mapping to canonical uArch columns #842

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Add PerfSpect 3.x and Zen5 metric name mapping to canonical uArch columns #842

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15 changes: 15 additions & 0 deletions perfpub/utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1142,11 +1142,13 @@ def process_metrics(
"TopDown FrontendBound %": "frontend_bound",
"Topdown Level 1/Frontend Bound": "frontend_bound",
"metric_TMA_Frontend_Bound(%)": "frontend_bound",
"TMA_Frontend_Bound(%)": "frontend_bound",
"Frontend Bound %": "frontend_bound",
"Topdown Level 1/Backend Bound": "backend_bound",
"Backend Stalls": "backend_bound",
"TopDown BackendBound %": "backend_bound",
"metric_TMA_Backend_Bound(%)": "backend_bound",
"TMA_Backend_Bound(%)": "backend_bound",
"Backend Bound %": "backend_bound",
"Avg. IPC": "IPC",
"IPC": "IPC",
Expand All @@ -1155,49 +1157,62 @@ def process_metrics(
"Branch Mispred %": "branch_mispred",
"Branch Effectiveness/Branch Misprediction Ratio": "branch_mispred",
"metric_TMA_..Branch_Mispredicts(%)": "branch_mispred",
"TMA_..Branch_Mispredicts(%)": "branch_mispred",
"Branch Retired Mispred PKI": "branch_mispred",
"L1 ICache MPKI (w/ prefetches)": "L1_icache_mpki",
"L1 ICache MPKI": "L1_icache_mpki",
"L1 Instruction Cache Effectiveness/L1I Cache MPKI": "L1_icache_mpki",
"metric_L1-I code read misses (w/ prefetches) per instr": "L1_icache_mpki",
"L1-I code read misses (w/ prefetches) per instr": "L1_icache_mpki",
"Any L1 IC Fills PKI": "L1_icache_mpki",
"L1 DCache MPKI (w/ prefetches)": "L1_dcache_mpki",
"L1 DCache MPKI": "L1_dcache_mpki",
"Misses Per Kilo Instructions/L1D Cache MPKI": "L1_dcache_mpki",
"metric_L1D MPI (includes data+rfo w/ prefetches)": "L1_dcache_mpki",
"L1D MPI (includes data+rfo w/ prefetches)": "L1_dcache_mpki",
"Any L1 DC Fills PKI": "L1_dcache_mpki",
"L2 Cache MPKI": "L2_cache_mpki",
"L2 Unified Cache Effectiveness/L2 Cache MPKI": "L2_cache_mpki",
"metric_L2 MPI (includes code+data+rfo w/ prefetches)": "L2_cache_mpki",
"L2 MPI (includes code+data+rfo w/ prefetches)": "L2_cache_mpki",
"LLC MPKI": "LLC_mpki",
"L3 Cache MPKI": "LLC_mpki",
"Last Level Cache Effectiveness/LL Cache Read MPKI": "LLC_mpki",
"metric_LLC MPI (includes code+data+rfo w/ prefetches)": "LLC_mpki",
"LLC MPI (includes code+data+rfo w/ prefetches)": "LLC_mpki",
"L3 MPKI": "LLC_mpki",
"iTLB MPKI": "iTLB_mpki",
"iTLB Walk MPKI": "iTLB_mpki",
"Instruction TLB Effectiveness/ITLB MPKI": "iTLB_mpki",
"metric_ITLB MPI": "iTLB_mpki",
"ITLB MPI": "iTLB_mpki",
"L1 iTLB Miss PKI": "iTLB_mpki",
"dTLB MPKI": "dTLB_mpki",
"dTLB Walk MPKI": "dTLB_mpki",
"Data TLB Effectiveness/DTLB MPKI": "dTLB_mpki",
"metric_DTLB load MPI": "dTLB_mpki",
"DTLB load MPI": "dTLB_mpki",
"L1 dTLB Miss PKI": "dTLB_mpki",
"TopDown Retiring %": "retiring",
"Topdown Level 1/Retiring": "retiring",
"metric_TMA_Retiring(%)": "retiring",
"TMA_Retiring(%)": "retiring",
"Retiring %": "retiring",
"Topdown Level 1/Bad Speculation": "bad_speculation",
"metric_TMA_Bad_Speculation(%)": "bad_speculation",
"TMA_Bad_Speculation(%)": "bad_speculation",
"TopDown bad Speculation %": "bad_speculation",
"TopDown Bad Speculation %": "bad_speculation",
"Bad Speculation %": "bad_speculation",
"L1 iCache MPKI": "L1_icache_mpki",
"L1 dCache MPKI": "L1_dcache_mpki",
"L2 Code MPKI": "L2_code_mpki",
"metric_L2 demand code MPI": "L2_code_mpki",
"L2 demand code MPI": "L2_code_mpki",
"L2 Cache Miss from IC Fill Miss PKI": "L2_code_mpki",
"L2 Data MPKI": "L2_data_mpki",
"metric_L2 demand data read MPI": "L2_data_mpki",
"L2 demand data read MPI": "L2_data_mpki",
}

amd_perf_collector = read_amd_perf_collector(
Expand Down