fix(esp_lvgl_port): support CONFIG_LCD_RGB_ISR_IRAM_SAFE for RGB panels (BSP-787)#732
fix(esp_lvgl_port): support CONFIG_LCD_RGB_ISR_IRAM_SAFE for RGB panels (BSP-787)#732matiasgibbons wants to merge 3 commits intoespressif:masterfrom
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When CONFIG_LCD_RGB_ISR_IRAM_SAFE is enabled on ESP32-S3, the VSYNC/bounce buffer callback must be placed in IRAM. The current implementation calls lv_display_get_driver_data() from the callback, which resides in flash. When SPI flash operations disable cache, this causes a LoadProhibited crash. Fix: when CONFIG_LCD_RGB_ISR_IRAM_SAFE is set, pass the disp_ctx struct directly as user_ctx instead of the lv_display_t pointer. This avoids any flash function calls from the ISR context. Without CONFIG_LCD_RGB_ISR_IRAM_SAFE the behavior is unchanged.
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Pull request overview
This PR updates the ESP LVGL port’s RGB panel VSYNC/bounce-buffer callback path to support CONFIG_LCD_RGB_ISR_IRAM_SAFE on ESP32-S3 by ensuring the callback can run safely with cache disabled (e.g., during SPI flash operations).
Changes:
- Adds an IRAM-safe variant of
lvgl_port_flush_rgb_vsync_ready_callback()guarded byCONFIG_LCD_RGB_ISR_IRAM_SAFE. - Passes
disp_ctxas the RGB panel callbackuser_ctxwhen IRAM-safe mode is enabled to avoid callinglv_display_get_driver_data()from ISR context. - Keeps the existing behavior unchanged when
CONFIG_LCD_RGB_ISR_IRAM_SAFEis disabled.
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- Replace assert() with null-check + early return in IRAM callback (assert references flash strings, defeating IRAM safety) - Allocate disp_ctx from internal RAM (MALLOC_CAP_INTERNAL) when CONFIG_LCD_RGB_ISR_IRAM_SAFE is enabled, ensuring the struct remains accessible when cache is disabled during SPI flash ops
…it compliance Use heap_caps_malloc with MALLOC_CAP_DEFAULT in the non-IRAM-safe path instead of plain malloc(). Functionally equivalent but satisfies the ESP-IDF pre-commit hook that forbids bare malloc() calls.
Problem
On ESP32-S3 with RGB LCD panels in bounce buffer mode, enabling
CONFIG_LCD_RGB_ISR_IRAM_SAFE=ycauses a LoadProhibited crash at boot:The root cause is that
lvgl_port_flush_rgb_vsync_ready_callback()callslv_display_get_driver_data(), which resides in flash. When SPI flashoperations disable the cache, the ISR tries to execute from flash → crash.
Without
CONFIG_LCD_RGB_ISR_IRAM_SAFE, the callback works but DMA underrunscan occur during flash operations, causing visible white horizontal lines on
the display (tearing artifacts).
Solution
When
CONFIG_LCD_RGB_ISR_IRAM_SAFEis enabled:IRAM_ATTRdisp_ctx(already in SRAM) directly asuser_ctxinstead ofdisp_drv(lv_display_t*), avoiding the need to calllv_display_get_driver_data()from ISR contextdisp_ctx->trans_semdirectly (xSemaphoreGiveFromISRis always in IRAM)When
CONFIG_LCD_RGB_ISR_IRAM_SAFEis not set, behavior is 100% unchanged.Testing
CONFIG_LCD_RGB_ISR_IRAM_SAFE=yNote
Medium Risk
Touches ESP32-S3 RGB panel ISR callback and display context allocation; mistakes could cause boot crashes or missed flush-ready signaling under cache-disabled conditions.
Overview
Fixes ESP32-S3 RGB panel flush completion handling when
CONFIG_LCD_RGB_ISR_IRAM_SAFEis enabled by moving the vsync/bounce-buffer callback into IRAM and avoiding flash-resident calls from ISR context.When IRAM safety is on, RGB panel event callbacks now receive
lvgl_port_display_ctx_t*directly asuser_ctx, and the display context is allocated from internal RAM (MALLOC_CAP_INTERNAL) so it remains accessible with cache disabled; behavior is unchanged when the config is off.Reviewed by Cursor Bugbot for commit 432f11d. Bugbot is set up for automated code reviews on this repo. Configure here.