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Unify differences of I2S hardware via metadata, add C5 and C61 I2S support #5483

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Merged
bugadani merged 9 commits into from
May 5, 2026
Merged

Unify differences of I2S hardware via metadata, add C5 and C61 I2S support #5483

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e89af24
Unify I2S hardware with metadata, add C5 and C61 I2S support
playfulFence Apr 30, 2026
9862c69
FMT + comment new I2S metadata flags
playfulFence Apr 30, 2026
79469a4
changlogs
playfulFence Apr 30, 2026
000e919
lint
playfulFence Apr 30, 2026
8ab1050
rename and unify two CONF1 related options
playfulFence May 4, 2026
4e8de68
Remove I2S-related constants, use clocks from metadata, clk_src to mdata
playfulFence May 4, 2026
680c9e2
separate conf1-conf different chips into v3
playfulFence May 4, 2026
89b2197
remap DMA channel to be based on dma_kind
playfulFence May 4, 2026
1c19985
rebase, fix `unused` warnings
playfulFence May 5, 2026
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1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
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Expand Up @@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Initial ESP32-P4 (chip revision v3.0+) support (#5400)
- P4: Initial peripheral support for GPIO, UART, I2C, SPI, DMA, USB Serial/JTAG, eFuse, SYSTIMER (#5400)
- P4: AP-HEX PSRAM driver stub with configurable HP L2MEM cache/RAM split via `ESP_HAL_CONFIG_L2_CACHE_SIZE` (#5400)
- C5 and C61: I2S support (#5483)

### Changed

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4 changes: 1 addition & 3 deletions esp-hal/README.md
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Expand Up @@ -80,7 +80,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
| HMAC | | | ⚒️ | [❌][5166] [^1] | ⚒️ | | ⚒️ | ❌ | ⚒️ | ⚒️ |
| I2C master | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ⚒️ | ✔️ | ✔️ |
| I2C slave | [❌][1909] [^1] | | [❌][1909] [^1] | [❌][1909] [^1] | [❌][1909] [^1] | [❌][1909] [^1] | [❌][1909] [^1] | ❌ | [❌][1909] [^1] | [❌][1909] [^1] |
| I2S | ⚒️ | | ⚒️ | [❌][5172] [^1] | ⚒️ | [❌][5415] [^1] | ⚒️ | ❌ | ⚒️ | ⚒️ |
| I2S | ⚒️ | | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ❌ | ⚒️ | ⚒️ |
| IEEE 802.15.4 | | | | ⚒️ | ⚒️ | | ⚒️ | | | |
| Interrupts | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ |
| IOMUX | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | | ⚒️ | ⚒️ |
Expand Down Expand Up @@ -141,8 +141,6 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
[5169]: https://github.com/esp-rs/esp-hal/issues/5169
[5170]: https://github.com/esp-rs/esp-hal/issues/5170
[5171]: https://github.com/esp-rs/esp-hal/issues/5171
[5172]: https://github.com/esp-rs/esp-hal/issues/5172
[5415]: https://github.com/esp-rs/esp-hal/issues/5415
[5417]: https://github.com/esp-rs/esp-hal/issues/5417
[5418]: https://github.com/esp-rs/esp-hal/issues/5418
[5419]: https://github.com/esp-rs/esp-hal/issues/5419
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2 changes: 1 addition & 1 deletion esp-hal/src/dma/mod.rs
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Expand Up @@ -2825,7 +2825,7 @@ pub(crate) mod asynch {
const FAILURE_INTERRUPTS: EnumSet<DmaTxInterrupt> =
enum_set!(DmaTxInterrupt::DescriptorError);

#[cfg_attr(any(esp32c2, esp32c61), expect(dead_code))]
#[cfg_attr(esp32c2, expect(dead_code))]
pub fn new(tx: &'a mut ChannelTx<Async, CH>) -> Self {
Self { tx }
}
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