Do not enter wfi when SBA access would not work

esp-hal/CHANGELOG.md

@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `RsaContext`, `AesContext` now derive `Clone`. (#4709)
 - `Sha<X>Context` now derive `Clone`, except on ESP32. (#4709)
 - Dedicated GPIO implementation (#4699)
+- `esp_hal::interrupt::wait_for_interrupt`, which enters `wfi` (RISC-V) or `waiti 0` (Xtensa) when it would not prevent a debugger from reading memory (#4782)
 
 ### Changed
 

esp-hal/src/interrupt/riscv.rs

@@ -14,8 +14,8 @@
 
 #[cfg(feature = "rt")]
 pub use esp_riscv_rt::TrapFrame;
 use procmacros::ram;
 use riscv::register::{mcause, mtvec};
 
 #[cfg(not(plic))]
 pub use self::classic::*;
@@ -357,7 +357,7 @@
 
 /// Get cpu interrupt assigned to peripheral interrupt
 #[inline]
 unsafe fn assigned_cpu_interrupt(interrupt: Interrupt) -> Option<CpuInterrupt> {
     let cpu_intr = INTERRUPT_CORE0::regs()
         .core_0_intr_map(interrupt as usize)
         .read()
@@ -370,17 +370,50 @@
     }
 }
 
 pub(crate) fn bound_cpu_interrupt_for(_cpu: Cpu, interrupt: Interrupt) -> Option<CpuInterrupt> {
     unsafe { assigned_cpu_interrupt(interrupt) }
 }
 
+fn cpu_wait_mode_on() -> bool {
+    cfg_if::cfg_if! {
+        if #[cfg(soc_has_pcr)] {
+            crate::peripherals::PCR::regs().cpu_waiti_conf().read().cpu_wait_mode_force_on().bit_is_set()
+        } else {
+            crate::peripherals::SYSTEM::regs()
+                .cpu_per_conf()
+                .read()
+                .cpu_wait_mode_force_on()
+                .bit_is_set()
+        }
+    }
+}
+
+/// Wait for an interrupt to occur.
+///
+/// This function causes the current CPU core to execute its Wait For Interrupt
+/// (WFI or equivalent) instruction. After executing this function, the CPU core
+/// will stop execution until an interrupt occurs.
+///
+/// This function will return immediately when a debugger is attached, so it is intended to be
+/// called in a loop.
+#[inline(always)]
+pub fn wait_for_interrupt() {
+    if crate::debugger::debugger_connected() && !cpu_wait_mode_on() {
+        // when SYSTEM_CPU_WAIT_MODE_FORCE_ON is disabled in WFI mode SBA access to memory does not
+        // work for debugger, so do not enter that mode when debugger is connected.
+        // https://github.com/espressif/esp-idf/blob/b9a308a47ca4128d018495662b009a7c461b6780/components/esp_hw_support/cpu.c#L57-L60
+        return;
+    }
+    unsafe { core::arch::asm!("wfi") };
+}
+
 mod vectored {
     use super::*;
     use crate::interrupt::IsrCallback;
 
     // Setup interrupts ready for vectoring
     #[doc(hidden)]
     pub(crate) unsafe fn init_vectoring() {
         for (num, prio) in PRIORITY_TO_INTERRUPT.iter().copied().zip(1..) {
             let which = unsafe { core::mem::transmute::<u32, CpuInterrupt>(num) };
             set_kind(Cpu::current(), which, InterruptKind::Level);
@@ -398,7 +431,7 @@
     /// Get the interrupts configured for the core at the given priority
     /// matching the given status
     #[inline]
     pub(crate) fn configured_interrupts(
         core: Cpu,
         status: InterruptStatus,
         priority: Priority,
@@ -496,7 +529,7 @@
 
     // First element is not used, just there to avoid a -1 in the interrupt handler.
     #[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
     pub(super) static INTERRUPT_TO_PRIORITY: [Priority; 16] = [
         Priority::None,
         Priority::Priority1,
         Priority::Priority2,
@@ -574,13 +607,13 @@
 
     /// Get interrupt priority
     #[inline]
     pub(super) fn priority_by_core(_core: Cpu, cpu_interrupt: CpuInterrupt) -> Priority {
         priority(cpu_interrupt)
     }
 
     /// Get interrupt priority - called by assembly code
     #[inline]
     pub(super) fn priority(cpu_interrupt: CpuInterrupt) -> Priority {
         let intr = INTERRUPT_CORE0::regs();
         unsafe {
             core::mem::transmute::<u8, Priority>(

esp-hal/src/interrupt/xtensa.rs

@@ -1,6 +1,6 @@
 //! Interrupt handling
 
 use procmacros::ram;
 use xtensa_lx::interrupt;
 #[cfg(esp32)]
 pub(crate) use xtensa_lx::interrupt::free;
@@ -96,7 +96,7 @@
 }
 
 impl CpuInterrupt {
     fn from_u32(n: u32) -> Option<Self> {
         if n < 32 {
             Some(unsafe { core::mem::transmute::<u32, Self>(n) })
         } else {
@@ -131,7 +131,7 @@
     CpuInterrupt::Interrupt22EdgePriority3 as _,
 ];
 
 pub(crate) fn setup_interrupts() {
     // disable all known interrupts
     // at least after the 2nd stage bootloader there are some interrupts enabled
     // (e.g. UART)
@@ -191,7 +191,7 @@
 }
 
 /// Get cpu interrupt assigned to peripheral interrupt
 pub(crate) fn bound_cpu_interrupt_for(cpu: Cpu, interrupt: Interrupt) -> Option<CpuInterrupt> {
     let cpu_intr = match cpu {
         Cpu::ProCpu => INTERRUPT_CORE0::regs()
             .core_0_intr_map(interrupt as usize)
@@ -291,6 +291,16 @@
     unwrap!(Priority::try_from(prev_interrupt_priority))
 }
 
+/// Wait for an interrupt to occur.
+///
+/// This function causes the current CPU core to execute its Wait For Interrupt
+/// (WFI or equivalent) instruction. After executing this function, the CPU core
+/// will stop execution until an interrupt occurs.
+#[inline(always)]
+pub fn wait_for_interrupt() {
+    unsafe { core::arch::asm!("waiti 0") };
+}
+
 mod vectored {
     use super::*;
 
@@ -345,7 +355,7 @@
 
     impl CpuInterrupt {
         #[inline]
         fn level(&self) -> Priority {
             match self {
                 CpuInterrupt::Interrupt0LevelPriority1
                 | CpuInterrupt::Interrupt1LevelPriority1
@@ -390,7 +400,7 @@
 
     /// Get the interrupts configured for the core
     #[inline(always)]
     pub(crate) fn configured_interrupts(
         core: Cpu,
         status: InterruptStatus,
         level: u32,

esp-rtos/CHANGELOG.md

@@ -29,6 +29,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Fixed a possible deadlock on multi-core chips (#4478)
 - Fixed a memory leak of 48 bytes when deleting esp-radio timers (#4541)
 - Fixed a rare crash on Xtensa MCUs (#4580, #4591)
+- RISC-V: the idle hook no longer prevents a debugger from reading memory (#4782)
 
 ### Removed
 

esp-rtos/src/task/mod.rs

@@ -33,6 +33,12 @@ use crate::{
 
 pub type IdleFn = extern "C" fn() -> !;
 
+pub(crate) extern "C" fn idle_hook() -> ! {
+    loop {
+        esp_hal::interrupt::wait_for_interrupt();
+    }
+}
+
 #[derive(Clone, Copy, PartialEq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub(crate) enum TaskState {

esp-rtos/src/task/riscv.rs

@@ -112,12 +112,6 @@ impl CpuContext {
     }
 }
 
-pub(crate) extern "C" fn idle_hook() -> ! {
-    loop {
-        unsafe { core::arch::asm!("wfi") };
-    }
-}
-
 pub(crate) fn set_idle_hook_entry(idle_context: &mut CpuContext, hook_fn: IdleFn) {
     // Point idle context PC at the assembly that calls the idle hook. We need a new stack
     // frame for the idle task on the main stack.

esp-rtos/src/task/xtensa.rs

@@ -36,12 +36,6 @@ use crate::{
 
 static IDLE_HOOK: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut());
 
-pub(crate) extern "C" fn idle_hook() -> ! {
-    loop {
-        unsafe { core::arch::asm!("waiti 0") };
-    }
-}
-
 #[unsafe(naked)]
 extern "C" fn idle_entry() -> ! {
     core::arch::naked_asm!("