Add NEON optimizations for SynetInnerProduct16bGemmNN - #822
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Port Base::SynetInnerProduct16bGemmNN to ARM/ARM64 NEON following the existing SSE4.1/SVE2 GemmNN patterns. Wire Init dispatch, tests, VS2022 Neon project files, and release notes for 7.2.165. Co-authored-by: Ihar Yermalayeu <ermig1979@gmail.com>
ermig1979
marked this pull request as ready for review
August 5, 2026 11:12
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Summary
Base::SynetInnerProduct16bGemmNNto ARM/ARM64 NEON (SimdNeonSynetInnerProduct16b.cpp,SimdNeonSynetInnerProduct16bGemmNN.cpp), following the existing SSE4.1 (fixed 128-bit) and SVE2 GemmNN patterns.SimdSynetInnerProduct16bInitdispatch,Test::SynetInnerProduct16bAutoTest, VS2022 Neon project files, and release notes indocs/2026.html(7.2.165).Implementation notes
F=4,microM=5,microN=8,microK=2(same tiling as SSE4.1).Neon::Float32ToBFloat16/Bf16::MASK; A broadcasts viaBroadcastBf16(same approach as SVE2).Activate<>with localSave1/Save2helpers (Term16bLast16b / Last32f / Interim).Validation
libSimd.so+Testsucceeded.qemu-aarch64-static,SynetInnerProduct16bAutoTest passed for Neon vs Base (default Release case + temporarily expanded aligned/unaligned/transpose cases covering Convert/Reorder A/B paths).SynetInnerProduct16bsmoke also passed (shared wiring still OK).