ts71xxweim: extend IRQ functionality for interrupt controller and gpio controller#275
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anakin-childerhose-sfl wants to merge 18 commits intoembeddedTS:linux-6.6.yfrom
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ts71xxweim: extend IRQ functionality for interrupt controller and gpio controller#275anakin-childerhose-sfl wants to merge 18 commits intoembeddedTS:linux-6.6.yfrom
anakin-childerhose-sfl wants to merge 18 commits intoembeddedTS:linux-6.6.yfrom
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Support both rev56 and rev65 of FPGA firmware by checking TSWEIM_IRQ_ACK_MODE_EN in TSWEIM_IRQ_ACK_MODE.
priv->mask by default will be initialized with 0. This may not accurately reflect the value in TSWEIM_IRQ_MASK. Initialize priv->mask with TSWEIM_IRQ_MASK to ensure the variable is synced with the register.
Since tsweim_intc_probe() uses platform_set_drvdata(), tsweim_intc_remove() should use platform_get_drvdata() instead of dev_get_platdata().
The driver was assigning the address of the local `priv` pointer to
`pdev->dev.platform_data`. This is incorrect for two reasons:
1. It assigns the address of a stack variable ("&priv") rather than the
allocated struct itself, leading to invalid memory access if used later.
2. The driver uses devm_gpiochip_add_data(), which handles private data
association internally. There is no need to manually set platform_data
or driver data in the probe function for this driver's usage patterns.
Follow the convention of allocating kernel memory first on driver probe.
Now that the private data is allocated before calling devm_ioremap(), the local variable membase is no longer needed.
The priv->syscon __iomem attribute gets populated with devm_ioremap(index = 0) which will return the cell at the 0th index of the reg property from the devicetree. This is the base register address of the fpga_gpio controller and not the register of the parent syscon device. Rename syscon to base to avoid this confusion.
…o devices The ts71xxweim-gpio driver will support interrupts via interrupt registers starting 0x4080 and incrementing by 0x10 per bank.
Add interrupt support to the WEIM FPGA GPIO driver. When an IRQ resource is present in the device tree, a second memory-mapped register range is used to configure and manage interrupts. The driver supports level-high, level-low, rising-edge, falling-edge, and both-edge trigger types. IRQ support is optional; if no IRQ is specified in the device tree the driver falls back to GPIO-only operation. Note: the optional irq_chip.mask_ack is intentionally omitted. Providing it triggers a WARN_ON in gpiochip_disable_irq.
Get a reference to the syscon node to check FPGA revision and ack_mode_en status to retain backwards compatiblity for boards with older FPGA revisions.
In newer revisions of the FPGA firmware the MASK register applies the mask to the status register in hardware. This removes the need to do so in software. Looping on the status register is also not required and could cause interrupt storms.
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irq-ts71xxweim changes
Changes made:
These commits have been tested on a ts7250 v3 with FPGA firmware rev70 by jumping the RX and TX pins together for the three RS-232 UARTS and running them all at 115200 baud for a period of time:
The output of linux-serial-test for each tty:
gpio-ts71xxweim changes
Changes made:
These commits have been tested on a ts7250 v3 with FPGA firmware rev70 by jumping two gpios together then using gpiomon on one to listen for interrupts and gpioset on the other to trigger interrupts.