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video: restore normal SG2002 video clocks for LT6911C/D - #474
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dormancygrace
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Reviewed against the latest #63 data from the C unit and the vendor drivers. One blocking regression and two questions about the premise.
What the C data shows. The 3.4.0 watch on the glitching C unit has ecc 65536. cif_isr (osdrv/interdrv/cif/chip/cv181x/cif.c) masks every CSI error interrupt once any counter exceeds 0xFFFF ("mask the interrupt since err cnt is full"). So crc 727 and wc 971 are frozen, not quiet. That is about one ECC error per second over ~17 h, plus CRC errors and short lines and frames. The UXC unit is clean on the same SoC clocks, and our PCIe UXC is clean even at 1080p90.
The three clocks here (vc_src0, axi_video_codec, src_vip_sys_1) are downstream of the CSI MAC, which runs from vip_sys2 (cif_set_mac_clk). They are the same on the clean UXC. So I don't see how they would change ECC/CRC errors on the receiver link. I'd want a C measurement (counters reset with echo reset 0 > /proc/mipi-rx before the watch) before shipping a lower profile.
Also unaddressed by this PR and #475: #349 drops only frames that the CSI bridge flags (isp_err_chk: short or long lines and frames, FIFO overflow). A frame with a CRC-damaged payload but the right size is never marked and is still encoded. The MIPI RX hs-settle (hs_s in /proc/mipi-rx, default 16) is the obvious knob for a link with ~1 ECC error/s. It can be swept live on the reporter's unit without a build.
Build outputsCompared with the build of main at ad056e1. 6 changed, 1 added, 0 removed of 571 outputs.
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Review follow-up verified on a7bd608. Unknown/late-model startup now has an explicit, tested DT deferral with a stopped-service detection retry; genuine profile failures remain blocked. Exclusive PLL references are released after the transition, including complete unwind on lookup/exclusivity/apply errors. All four threads are answered/resolved. Automatic stock selection for both C and D is retained at the user's explicit direction.
Local validation passes: production clock/module/startup/native gates normally and with ASan/UBSan, three runtime negative controls, related capture/startup/model/package/receiver contracts, real APK dependency solving, external 7.3-r3 module cross-build and complete GCC 16.2 capture cross-link. CI is running for this final head.
The diagnostic objection is valid and is not considered solved by this policy: vendor cif.c masks the CSI error interrupts when any error counter exceeds 0xFFFF, so frozen CRC/WC counts after ECC=65536 are not evidence of a quiet link. These three downstream processing clocks do not constitute a demonstrated explanation for CSI ECC/CRC. No hs-settle/PHY change or CRC-payload rejection is introduced here, and #63 remains unresolved. Physical C/D measurements are still required; the available local UXC stand cannot qualify C/D frequencies.
LT6911C and LT6911D automatically select 396/360/300 MHz for vc_src0, axi_video_codec and src_vip_sys_1 instead of the 594/450/396 MHz DT profile. The values follow the normal-mode branch of Sipeed's pinned sys_pll_nd source. UXC/UE retain their existing profile. Automatic selection for both C and D is the explicitly requested policy; D was reported unaffected by the C fault.
Before both video services start, the helper retries missing/unknown model detection. A successful retry applies the C/D profile before capture. If detection still fails, an explicit RAM policy marker preserves the DT profile for that service run, including late native identification; the next stopped service start selects stock automatically. A known profile failure stays blocked and cannot be relabelled as unidentified. Management services remain available.
The CCF module changes and verifies muxes/dividers without retuning PLLs or transiently overclocking AXI. Exclusive PLL references protect only the stopped transition, then are released; child exclusivity is avoided because CCF propagates it to ancestors. Native admission verifies receiver, readiness and live rates before every capture open/reopen. Package capabilities require both helper and module on application-only upgrades.
Validation on a7bd608: six production clock/model/module/startup/admission tests pass normally and with ASan/UBSan; module lookup, exclusivity and transition failure paths release every reference. Three runtime negative controls detect unknown-startup refusal, late-native refusal and persistent PLL protection. Related restart/startup/model/platform/package/receiver/native contracts pass, including real APK solving and native ASan/UBSan contracts. The external module cross-builds for 7.3.0-nanokvm-os-r3 and the complete capture library cross-links with GCC 16.2.
Physical C/D qualification is pending because the local stand is UXC. These are source-defined normal clocks for three processing domains; the reporter's factory register values are unmeasured. Lower clocks can reduce scaling/encoding throughput. This policy does not establish the cause of #63 or claim to fix its CSI ECC/CRC errors. Firmware, EDID, CSI PHY timing and polling are unchanged. The pinmux experiment remains separate in #475.