A Boolean Logic Synthesis Engine
Kiln is a Rust-based tool for synthesizing Boolean logic into digital circuit representations for FPGAs (Field Programmable Gate Arrays) and ASICs (Application-Specific Integrated Circuits). It parses Boolean expressions, generates truth tables, and applies minimization techniques, including the Quine-McCluskey algorithm and Karnaugh Map (up to 4 variables), to optimize logic. Kiln outputs synthesizable HDL (Hardware Description Language) code in Verilog and VHDL, supporting behavioral, dataflow, and structural styles, along with testbenches for verification. It includes analysis features like timing, area estimation, and technology mapping, with customizable optimization for speed, area, or power. With a CLI (command-line interface), proper error handling, and over 100 unit tests, Kiln is a practical tool for digital circuit design and education.
- Expression Parsing: Robust Boolean expression parser with operator precedence
- Truth Table Generation: Automatic truth table creation from expressions
- Logic Minimization: Multiple state-of-the-art algorithms:
- Quine-McCluskey Algorithm (exact minimization)
- Karnaugh Map Minimization (up to 4 variables)
- Canonical Form Conversion (SOP/POS)
- Verilog Generation: IEEE 1364-compliant Verilog modules
- VHDL Generation: IEEE 1076-compliant VHDL entities
- Multiple Styles: Behavioral, Dataflow, Structural, and Mixed
- Testbench Generation: Comprehensive testbenches with multiple strategies
- Timing Analysis: Critical path analysis and timing constraint verification
- Area Estimation: Resource utilization and optimization suggestions
- Technology Mapping: Gate library mapping with optimization targets
- Performance Benchmarking: Detailed optimization statistics and metrics
- Comprehensive Error Handling: Detailed error messages with suggestions
- Configurable Optimization: Multiple optimization targets (speed, area, power)
- Extensive Testing: 100+ unit tests covering all major functionality
- Command-Line Interface: Full-featured CLI with multiple output formats
- Rust 1.70 or later
- Cargo (comes with Rust)
git clone https://github.com/yourusername/kiln.git
cd kiln
cargo build --releaseThe binary will be available at target/release/kiln.
# Linux/macOS
export PATH="$PATH:$(pwd)/target/release"
# Windows (PowerShell)
$env:PATH += ";$(pwd)\target\release"Note: The examples below use
cargo run --for development. After installation, you can replacecargo run --withkilnfor the official command.Development:
cargo run -- minimize 'A & B'
Installed:kiln minimize 'A & B'
parse - Parse and analyze Boolean expressions
cargo run -- parse 'A & B | C' --show-ast --truth-tableValidates syntax, shows AST structure, and optionally generates truth table
truth-table - Generate truth tables from expressions
cargo run -- truth-table 'A | B & C' --format table
cargo run -- truth-table 'A & B' --format csv --save results.csvCreates comprehensive truth tables in multiple formats (table/csv/json)
minimize - Minimize Boolean expressions
cargo run -- minimize 'A & B | A & !B' --algorithm quine-mccluskey --stats
cargo run -- minimize 'A & B | C & D' --algorithm karnaugh-map --stepsReduces expressions using Quine-McCluskey or Karnaugh Map algorithms
generate - Generate hardware description language output
cargo run -- generate 'A & B | C' --language verilog --module-name logic_unit
cargo run -- generate 'A | B' --language vhdl --testbench --minimizeCreates Verilog/VHDL modules with optional testbenches and pre-minimization
timing - Perform timing analysis
cargo run -- timing 'A & B & C' --frequency 500 --library high-performance --reportAnalyzes critical paths and timing constraints for target frequencies
area - Estimate area and resource usage
cargo run -- area 'A & B | C' --technology 45 --detailedCalculates gate count, silicon area, and resource utilization
synthesize - Complete synthesis flow
cargo run -- synthesize 'A & B | !A & C' --language both --frequency 100 --allEnd-to-end synthesis with minimization, HDL generation, and analysis
--verbose- Enable detailed output--output-dir <path>- Set output directory--no-color- Disable colored output
Let's walk through designing a simple ALU control unit using Kiln's commands:
We want to create control logic that selects between ADD (A&B) and OR (A|B) operations based on a select signal S.
# Our control expression: if S then (A & B) else (A | B)
# Boolean form: S & A & B | !S & (A | B)
$ cargo run -- parse 'S & A & B | !S & (A | B)' --show-ast
✅ Expression parsed successfully in 3.14ms
🌳 Abstract Syntax Tree:
Or(
And(
And(
Variable(
"S",
),
Variable(
"A",
),
),
Variable(
"B",
),
),
And(
Not(
Variable(
"S",
),
),
Or(
Variable(
"A",
),
Variable(
"B",
),
),
),
)$ cargo run -- truth-table 'S & A & B | !S & (A | B)' --format table
📊 Truth Table Generation:
Variables: [A, B, S]
| A | B | S | Output |
|---|---|---|--------|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 |
$ cargo run -- minimize 'S & A & B | !S & (A | B)' --algorithm quine-mccluskey --stats
🎯 Quine-McCluskey Minimization Result:
A & !S + A & B + B & !S
📊 Optimization Statistics:
Algorithm: Quine-McCluskey | Time: 3.51ms | Gates: 6 → 7 (-16.7% reduction) | Literals: 6 → 6 (0.0% reduction) | Effectiveness: 0.0%
$ cargo run -- generate 'A & !S | A & B | B & !S' --language verilog --module-name alu_control --testbench
📄 Generated Verilog module: ./alu_control.v
🧪 Generated testbench: ./alu_control_tb.v
$ cat alu_control.v
module alu_control (
input A,
input B,
input S,
output result
);
// Input signals
// A: Boolean input variable
// B: Boolean input variable
// S: Boolean input variable
// result: Combined logic output
// Dataflow implementation using assign statement
assign result = (A & ~B & ~S) | (~A & B & ~S) | (A & B & ~S) | (A & B & S);
endmodule$ cargo run -- synthesize 'A & !S | A & B | B & !S' --language verilog --module-name alu_control --frequency 100 --all
🚀 Starting complete synthesis flow for: A & !S | A & B | B & !S
📄 Generated: ./alu_control.v
🎯 Synthesis Summary:
Expression: A & !S | A & B | B & !S
Module: alu_control
Technology: 180nm
Target Frequency: 100.0 MHz
⚡ Optimization Results:
Algorithm: Complete Synthesis | Time: 48.07ms | Gates: 7 → 7 (0.0% reduction) | Literals: 6 → 6 (0.0% reduction) | Effectiveness: 0.0%
⏱️ Timing Results:
Critical Path: 1.87 ns
Max Frequency: 404.9 MHz
Timing: ✅ MET
📐 Area Results:
Total Area: 19.13 µm²
Gate Count: 7
Efficiency: 64.8%
✅ Synthesis completed successfully in 48.07ms# Emergency (E) OR (Green phase (G) AND Timer (T))
$ cargo run -- minimize 'E | G & T' --stats
$ cargo run -- generate 'E | G & T' --language vhdl --module-name traffic_ctrl# Enable AND (Address A1,A0): EN & (!A1 & !A0 | !A1 & A0 | A1 & !A0 | A1 & A0)
$ cargo run -- minimize 'EN & (!A1 & !A0)' --algorithm karnaugh-map
$ cargo run -- truth-table 'EN & A1 & A0' --format csv --save decoder.csvLogic Design Challenges:
- Design a 3-input majority function:
(A & B) | (B & C) | (A & C) - Create a parity checker:
A ^ B ^ C ^ D(use!((A & B & C & D) | (!A & !B & !C & !D))) - Build a multiplexer:
S & A | !S & B
Analysis Experiments:
- Compare Quine-McCluskey vs Karnaugh Map on the same 4-variable expression
- Generate both Verilog and VHDL for the same logic and compare
- Test timing analysis at different frequencies (10MHz, 100MHz, 1GHz)
Synthesis Flows:
- Start with a complex expression, minimize it, then generate optimized HDL
- Create truth tables for debugging, then synthesize working hardware
- Use area analysis to optimize for different technology nodes
Kiln includes a test suite covering all major functionality:
# Run all tests
cargo test
# Run with output
cargo test -- --nocapture
# Run specific test module
cargo test --test parsing_tests
cargo test --test karnaugh_map_tests
cargo test --test generation_tests
# Run benchmarks
cargo benchThis project is licensed under the MIT License, see the LICENSE file for details.
For questions, suggestions, or support, please open an issue on GitHub.