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[6.6] Add support for Hygon family 18h model 18h #1629

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Merged
opsiff merged 11 commits into from
Apr 16, 2026
Merged

[6.6] Add support for Hygon family 18h model 18h #1629

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d63e3e1
EDAC/amd64: Convert Hygon family 18h model checks to switch-case
liaoxuan123 Jan 29, 2026
a5c7833
EDAC/amd64: Add support for Hygon family 18h model 18h
liaoxuan123 Mar 16, 2026
0069ab2
EDAC/amd64: Adjust the maximum number of memory controllers per node …
liaoxuan123 Mar 25, 2026
d1b21e6
ALSA: hda: Add support for Hygon family 18h model 18h HD-Audio
liaoxuan123 Jan 27, 2026
6ac8660
x86/amd_nb: Add Hygon family 18h model 18h PCI IDs
liaoxuan123 Jan 26, 2026
2249df6
hwmon/k10temp: Add support for Hygon family 18h model 18h
liaoxuan123 Jan 27, 2026
adae0b3
iommu/hygon: Add support for Hygon family 18h model 18h IOAPIC
liaoxuan123 Jan 27, 2026
f20332b
mmc: sdhci-acpi: Add device HID for Hygon eMMC controller
liaoxuan123 Jan 27, 2026
4f1852d
mmc: sdhci-pci: Add support for Hygon SD controller
liaoxuan123 Jan 27, 2026
c8241cf
spi: dw: Add device HID for Hygon SPI controller
liaoxuan123 Jan 27, 2026
111396b
perf/x86/uncore: Add DF PMU support for Hygon family 18h model 18h
liaoxuan123 Jan 27, 2026
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6 changes: 2 additions & 4 deletions arch/x86/events/amd/uncore.c
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Original file line number Diff line number Diff line change
Expand Up @@ -742,10 +742,8 @@ static int __init amd_uncore_init(void)
if (boot_cpu_data.x86_model == 0x4 ||
boot_cpu_data.x86_model == 0x5)
*df_attr++ = &format_attr_umask10f18h.attr;
else if (boot_cpu_data.x86_model == 0x6 ||
boot_cpu_data.x86_model == 0x7 ||
boot_cpu_data.x86_model == 0x8 ||
boot_cpu_data.x86_model == 0x10)
else if (boot_cpu_data.x86_model >= 0x6 &&
boot_cpu_data.x86_model <= 0x18)
*df_attr++ = &format_attr_umask12f18h.attr;
}

Expand Down
5 changes: 5 additions & 0 deletions arch/x86/kernel/amd_nb.c
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Expand Up @@ -47,10 +47,12 @@

#define PCI_DEVICE_ID_HYGON_18H_M05H_ROOT 0x14a0
#define PCI_DEVICE_ID_HYGON_18H_M10H_ROOT 0x14c0
#define PCI_DEVICE_ID_HYGON_18H_M18H_ROOT 0x2000
#define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1 0x1491
#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1 0x14b1
#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F4 0x14b4
#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F4 0x14d4
#define PCI_DEVICE_ID_HYGON_18H_M18H_DF_F4 0x2014
#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F5 0x14b5
Comment on lines 48 to 56
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Copilot AI Apr 15, 2026

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These new #define lines introduce stray whitespace before the tab/value alignment (visible trailing spaces). Please align with surrounding defines using a single tab after the macro name and avoid trailing spaces so checkpatch/style tools don't flag it.

Copilot uses AI. Check for mistakes.

/* Protect the PCI config register pairs used for SMN. */
Expand Down Expand Up @@ -139,6 +141,7 @@ static const struct pci_device_id hygon_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M18H_ROOT) },
{}
};

Expand All @@ -147,6 +150,7 @@ static const struct pci_device_id hygon_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M10H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M18H_DF_F3) },
{}
};

Expand All @@ -155,6 +159,7 @@ static const struct pci_device_id hygon_nb_link_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M10H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M18H_DF_F4) },
{}
};

Expand Down
52 changes: 41 additions & 11 deletions drivers/edac/amd64_edac.c
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Expand Up @@ -107,6 +107,29 @@ static u32 get_umc_base_f18h_m4h(u16 node, u8 channel)
return get_umc_base(channel) + (0x80000000 + (0x10000000 * df_id));
}

static u32 get_umc_base_f18h_m18h(u8 channel)
{
return 0x70000000 + (channel << 20);
}

static u32 hygon_get_umc_base(struct amd64_pvt *pvt, u8 channel)
{
u32 umc_base;

if (hygon_f18h_m4h())
umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, channel);
/*
* For Hygon family 18h model 0x18h-0x1fh processors, the UMC base
* are identical.
*/
else if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18)
umc_base = get_umc_base_f18h_m18h(channel);
else
umc_base = get_umc_base(channel);

return umc_base;
Comment on lines +117 to +130
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Copilot AI Apr 15, 2026

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New hygon_get_umc_base() block uses space indentation instead of kernel-style tabs, and the comment has grammar issues ("UMC base are"). Also, the new Hygon UMC base selection is only wired into umc_read_base_mask()/umc_read_mc_regs(); umc_dump_misc_regs() still uses the old m4h-only special case and would read wrong registers on F18h M18h (and any other Hygon models that need a non-default base). Consider switching umc_dump_misc_regs() to use the same helper so all UMC register reads stay consistent.

Suggested change
u32 umc_base;
if (hygon_f18h_m4h())
umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, channel);
/*
* For Hygon family 18h model 0x18h-0x1fh processors, the UMC base
* are identical.
*/
else if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18)
umc_base = get_umc_base_f18h_m18h(channel);
else
umc_base = get_umc_base(channel);
return umc_base;
if (hygon_f18h_m4h())
return get_umc_base_f18h_m4h(pvt->mc_node_id, channel);
/*
* For Hygon family 18h model 0x18-0x1f processors, the UMC base
* addresses are identical.
*/
if (hygon_f18h_m10h() && boot_cpu_data.x86_model >= 0x18)
return get_umc_base_f18h_m18h(channel);
return get_umc_base(channel);

Copilot uses AI. Check for mistakes.
}

/*
* Select DCT to which PCI cfg accesses are routed
*/
Expand Down Expand Up @@ -1812,8 +1835,8 @@ static void umc_read_base_mask(struct amd64_pvt *pvt)
if (!hygon_umc_channel_enabled(pvt, umc))
continue;

if (hygon_f18h_m4h())
umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, umc);
if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
umc_base = hygon_get_umc_base(pvt, umc);
else
umc_base = get_umc_base(umc);

Expand Down Expand Up @@ -3286,8 +3309,8 @@ static void umc_read_mc_regs(struct amd64_pvt *pvt)
if (!hygon_umc_channel_enabled(pvt, i))
continue;

if (hygon_f18h_m4h())
umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
umc_base = hygon_get_umc_base(pvt, i);
else
umc_base = get_umc_base(i);

Expand Down Expand Up @@ -4210,28 +4233,35 @@ static int per_family_init(struct amd64_pvt *pvt)
break;

case 0x18:
if (pvt->model == 0x4) {
switch (pvt->model) {
case 0x4:
pvt->ctl_name = "F18h_M04h";
pvt->max_mcs = 3;
break;
} else if (pvt->model == 0x5) {
case 0x5:
pvt->ctl_name = "F18h_M05h";
pvt->max_mcs = 1;
break;
} else if (pvt->model == 0x6) {
case 0x6:
pvt->ctl_name = "F18h_M06h";
break;
} else if (pvt->model == 0x7) {
case 0x7:
pvt->ctl_name = "F18h_M07h";
break;
} else if (pvt->model == 0x8) {
case 0x8:
pvt->ctl_name = "F18h_M08h";
break;
} else if (pvt->model == 0x10) {
case 0x10:
pvt->ctl_name = "F18h_M10h";
break;
case 0x18:
pvt->ctl_name = "F18h_M18h";
pvt->max_mcs = 1;
break;
default:
pvt->ctl_name = "F18h";
break;
}
pvt->ctl_name = "F18h";
break;

case 0x19:
Expand Down
1 change: 1 addition & 0 deletions drivers/hwmon/k10temp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -652,6 +652,7 @@ static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M10H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M18H_DF_F3) },
{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);
Expand Down
2 changes: 1 addition & 1 deletion drivers/iommu/amd/init.c
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Expand Up @@ -3054,7 +3054,7 @@ static bool __init check_ioapic_information(void)
(boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
boot_cpu_data.x86 == 0x18 &&
boot_cpu_data.x86_model >= 0x4 &&
boot_cpu_data.x86_model <= 0x10 &&
boot_cpu_data.x86_model <= 0x18 &&
devid == IOAPIC_SB_DEVID_FAM18H_M4H)) {
Comment on lines 3054 to 3058
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The condition now applies the IOAPIC_SB_DEVID_FAM18H_M4H workaround up to model 0x18, but the surrounding comment/identifier still says it's specific to model 4h. Please update the comment (and/or the constant name) so the code and documentation match the broadened model range.

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has_sb_ioapic = true;
ret = true;
Expand Down
2 changes: 2 additions & 0 deletions drivers/mmc/host/sdhci-acpi.c
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Expand Up @@ -700,6 +700,7 @@ static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
{ "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
{ "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
{ "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc },
{ "HYGO0040", NULL, &sdhci_acpi_slot_amd_emmc },
{ },
};

Expand All @@ -718,6 +719,7 @@ static const struct acpi_device_id sdhci_acpi_ids[] = {
{ "QCOM8052" },
{ "AMDI0040" },
{ "AMDI0041" },
{ "HYGO0040" },
{ },
};
MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
Expand Down
1 change: 1 addition & 0 deletions drivers/mmc/host/sdhci-pci-core.c
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Expand Up @@ -1942,6 +1942,7 @@ static const struct pci_device_id pci_ids[] = {
SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
SDHCI_PCI_DEVICE_CLASS(HYGON, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
/* Generic SD host controller */
{PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
{ /* end: all zeroes */ },
Expand Down
1 change: 1 addition & 0 deletions drivers/spi/spi-dw-mmio.c
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Expand Up @@ -439,6 +439,7 @@ MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
{"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
{"HYGO0062", (kernel_ulong_t)dw_spi_hssi_init},
{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
Expand Down
2 changes: 2 additions & 0 deletions include/linux/pci_ids.h
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Expand Up @@ -2602,8 +2602,10 @@
#define PCI_VENDOR_ID_HYGON 0x1d94
#define PCI_DEVICE_ID_HYGON_18H_M05H_HDA 0x14a9
#define PCI_DEVICE_ID_HYGON_18H_M10H_HDA 0x14c9
#define PCI_DEVICE_ID_HYGON_18H_M18H_HDA 0x2007
#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3 0x14b3
#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F3 0x14d3
#define PCI_DEVICE_ID_HYGON_18H_M18H_DF_F3 0x2013

#define PCI_VENDOR_ID_FUNGIBLE 0x1dad

Expand Down
2 changes: 2 additions & 0 deletions sound/pci/hda/hda_intel.c
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Expand Up @@ -2926,6 +2926,8 @@ static const struct pci_device_id azx_ids[] = {
.driver_data = AZX_DRIVER_HYGON | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_NO_MSI },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M10H_HDA),
.driver_data = AZX_DRIVER_HYGON },
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M18H_HDA),
.driver_data = AZX_DRIVER_HYGON | AZX_DCAPS_POSFIX_LPIB },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, azx_ids);
Expand Down
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