[WIP] [linux-6.6.y] [Upstream] arm64: Backport sysreg/cpufeature/PMU infrastructure from mainline (v6.7–v6.18) for CCA prerequisite （001） by Avenger-285714 · Pull Request #1615 · deepin-community/kernel

Avenger-285714 · 2026-04-13T03:02:15Z

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Copilot

Pull request overview

Backport of arm64 sysreg/cpufeature/PMU/KVM (incl. nested virt) infrastructure from newer mainline kernels as a prerequisite for CCA-related work, plus related CoreSight tracing and hwcap documentation updates.

Changes:

Updates Arm PMUv3 infrastructure to support newer PMU versions/counter layouts (incl. instruction counter, wider masks) and adjusts KVM PMU handling accordingly.
Refreshes KVM/VGIC trap handling and hyp switch paths (VHE/nVHE/pKVM), including new sysreg/feature plumbing and ESR decoding helpers.
Extends CoreSight TRBE/ETM handling and updates arm64 hwcap docs/definitions and sysreg header generation tooling.

Reviewed changes

Copilot reviewed 40 out of 42 changed files in this pull request and generated 7 comments.

Show a summary per file

File	Description
include/linux/perf/arm_pmuv3.h	Updates PMUv3 constants/masks; adds new bits and pulls in arch PMUv3 helpers
include/linux/perf/arm_pmu.h	Raises max HW events on arm64 to accommodate 33 counters
drivers/perf/arm_pmuv3.c	Reworks counter indexing/masks, adds instr counter handling, adjusts user-access enabling and IRQ handling
drivers/irqchip/irq-apple-aic.c	Updates GIC sysreg bit naming for ICH_HCR_EL2
drivers/hwtracing/coresight/coresight-trbe.c	Adds KVM integration hooks and changes buffer allocation/remove handling
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c	Updates TRFCR field naming used for timestamp source reporting
drivers/hwtracing/coresight/coresight-etm4x-core.c	Adds guest/host trace filtering integration with KVM; refactors enable/disable paths and mode handling
Documentation/arch/arm64/elf_hwcaps.rst	Updates hwcap descriptions and removes AT_HWCAP3 references in this doc
Documentation/arch/arm64/cpu-feature-registers.rst	Documents additional ZFR0 field (B16B16)
arch/arm64/tools/gen-sysreg.awk	Extends sysreg generator (prefix support, stricter validation, new syntax)
arch/arm64/mm/proc.S	Substantial MMU/KPTI/idmap and TCR/TCR2 setup refactoring and LPA2/VA52 handling
arch/arm64/kvm/vgic/vgic-v3.c	Updates VGIC register field usage; adds helper to compose ICH_HCR traps
arch/arm64/kvm/vgic-sys-reg-v3.c	Converts to new ICH_VTR_EL2 field macros for SEIS/A3V
arch/arm64/kvm/pmu.c	Widens PMU event tracking masks and uses PMUv3 “*_n” helpers for PMEVTYPER accesses
arch/arm64/kvm/hyp/vhe/switch.c	Large VHE hyp switch/exit handling refactor, including nested virt and sysreg fast paths
arch/arm64/kvm/hyp/vgic-v3-sr.c	Refactors VMCR/APR save/restore; improves trap activation behaviour
arch/arm64/kvm/hyp/nvhe/switch.c	Refactors nVHE trap activation and FP/SVE host-save logic; adjusts exit handler wiring
arch/arm64/kvm/hyp/nvhe/pkvm.c	Refactors pKVM vCPU trap/feature init, vtcr plumbing, and cache maintenance on donation unmap
arch/arm64/kvm/hyp/nvhe/mem_protect.c	Updates HPFAR decoding to FIELD_GET(HPFAR_EL2_FIPA)
arch/arm64/kvm/hyp/nvhe/hyp-main.c	Adds explicit FP/SVE sync paths for pKVM and updates vCPU sync/flush sequencing
arch/arm64/kvm/handle_exit.c	Adds nested forwarding for select traps; new OTHER/GCS handling and improved panic reporting
arch/arm64/kvm/fpsimd.c	Refactors host/guest FP ownership tracking, SME/SVE handling, and state sync points
arch/arm64/kernel/cpuinfo.c	Adds new hwcap strings for SVE_B16B16/LRCPC3/LSE128
arch/arm64/include/uapi/asm/hwcap.h	Adds new HWCAP2 bits for SVE_B16B16/LRCPC3/LSE128
arch/arm64/include/asm/sysreg.h	Refreshes sysreg definitions (incl. new PMU sysregs), removes some legacy macros
arch/arm64/include/asm/kvm_nested.h	Adds extensive nested-virt helpers (translation helpers, TLBI checks, S2 walk interfaces)
arch/arm64/include/asm/kvm_emulate.h	Adds nested trap injection helpers and CPACR/CPTR translation/trap utilities
arch/arm64/include/asm/kvm_arm.h	Maps legacy HCR bit names to new nomenclature; updates FGT/HCRX related masks
arch/arm64/include/asm/hwcap.h	Adds kernel hwcap feature indices for new HWCAP2 bits
arch/arm64/include/asm/esr.h	Adds new ESR EC/ISS definitions and helper predicates (fault classification, ERETAX helpers, etc.)
arch/arm64/include/asm/el2_setup.h	Updates EL2 init: HCRX GCS enabling, FGT changes, CPTR init changes, adds MPAM/GCS init
arch/arm64/include/asm/arm_pmuv3.h	Adds PMUv3 helpers (icntr, pmcc/pmic filters, u64 masks) and header include change
arch/arm/include/asm/arm_pmuv3.h	Adds stubs/defs for icntr and PMUv3p9 helpers on 32-bit Arm

Comments suppressed due to low confidence (1)

drivers/hwtracing/coresight/coresight-etm4x-core.c:2438

etm4_remove_platform_dev() was changed to return void, but the platform_driver still assigns it to .remove (which is an int-returning callback; the void form should be wired via .remove_new). This causes a function-pointer type mismatch and can fail builds with strict warning settings. Either restore an int return type (return 0) or use .remove_new in the driver struct.

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Copilot · 2026-04-13T03:09:59Z

 	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
 	if (!buf)
-		return NULL;
+		return ERR_PTR(-ENOMEM);

 	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
 	if (!pglist) {
 		kfree(buf);
-		return NULL;
+		return ERR_PTR(-ENOMEM);
 	}

 	for (i = 0; i < nr_pages; i++)
 		pglist[i] = virt_to_page(pages[i]);

 	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
 	if (!buf->trbe_base) {
 		kfree(pglist);
 		kfree(buf);
-		return NULL;
+		return ERR_PTR(-ENOMEM);
 	}


arm_trbe_alloc_buffer() returns ERR_PTR(-ENOMEM) on allocation failures, but coresight-etm-perf checks only for NULL ("if (!snk_config)") when calling sink_ops->alloc_buffer(). Returning ERR_PTR here will be treated as success and later dereferenced, leading to crashes. Return NULL on failure (consistent with other sinks like ETB/TMC), or update the core to use IS_ERR_OR_NULL (but that would be a broader change).

Copilot · 2026-04-13T03:09:59Z

+	desc.pdata = devm_kzalloc(dev, sizeof(*desc.pdata), GFP_KERNEL);
 	if (IS_ERR(desc.pdata))
 		goto cpu_clear;


devm_kzalloc() returns NULL on allocation failure, not an ERR_PTR. Checking IS_ERR(desc.pdata) will miss failures and can lead to passing a NULL pdata into coresight_register(). Use a NULL check here instead (and keep the cpu_clear path).

Copilot · 2026-04-13T03:10:00Z

@@ -1537,14 +1559,23 @@
 };
 MODULE_DEVICE_TABLE(of, arm_trbe_of_match);

+#ifdef CONFIG_ACPI
+static const struct platform_device_id arm_trbe_acpi_match[] = {
+	{ ARMV8_TRBE_PDEV_NAME, 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(platform, arm_trbe_acpi_match);
+#endif
+
 static struct platform_driver arm_trbe_driver = {
+	.id_table = ACPI_PTR(arm_trbe_acpi_match),
 	.driver	= {
 		.name = DRVNAME,
 		.of_match_table = of_match_ptr(arm_trbe_of_match),
 		.suppress_bind_attrs = true,
 	},
 	.probe	= arm_trbe_device_probe,
-	.remove	= arm_trbe_device_remove,
+	.remove = arm_trbe_device_remove,
 };


arm_trbe_device_remove() was changed to return void, but struct platform_driver still expects .remove to be an int-returning callback (with a separate .remove_new for void callbacks). Assigning this void function to .remove will cause a function-pointer type mismatch (often a build error under kernel warning settings). Either restore an int return type (return 0) or wire it up via .remove_new.

Copilot · 2026-04-13T03:10:00Z

 	mov_q	x0, PIE_E0
 	msr	REG_PIRE0_EL1, x0
 	mov_q	x0, PIE_E1
 	msr	REG_PIR_EL1, x0

-	orr	tcr2, tcr2, TCR2_EL1x_PIE
+#undef PTE_MAYBE_NG
+#undef PTE_MAYBE_SHARED
+
+	orr	tcr2, tcr2, TCR2_EL1_PIE
+	msr	REG_TCR2_EL1, x0


In __cpu_setup(), after setting TCR2_EL1_PIE in tcr2, the code writes REG_TCR2_EL1 using x0 (which currently holds PIE_E1), not tcr2. This will program TCR2_EL1 with an unrelated value when S1PIE is present but TCRX is absent, breaking address translation setup. Write tcr2 to REG_TCR2_EL1 here (and avoid the redundant/contradictory write later).

Copilot · 2026-04-13T03:10:00Z

+$1 == "EndPrefix" && block_current() == "Prefix" {
+	expect_fields(1)
+	if (next_bit >= 0)
+		fatal("Unspecified bits in prefix " prefix " for " reg)
+
+	define_resx_unkn(prefix, reg, res0, res1, unkn)
+
+	prefix = null
+	res0 = "UL(0)"
+	res1 = "UL(0)"
+	unkn = "UL(0)"
+	next_bit = 63
+
+	block_pop()
+
 	next
 }


gen-sysreg.awk calls define_resx_unkn(prefix, reg, res0, res1, unkn) in the EndPrefix handler, but there is no define_resx_unkn() function in this script. This will make the generator fail at runtime when processing a Prefix block. Either add an implementation (mirroring the EndSysreg/EndSysregFields emission of *_RES0/_RES1/_UNKN) or inline the required define() calls here.

Copilot · 2026-04-13T03:10:00Z

+#define ARMV8_PMU_USERENR_UEN	(1 << 4) /* Fine grained per counter access at EL0 */
 /* Mask for writable bits */
 #define ARMV8_PMU_USERENR_MASK	(ARMV8_PMU_USERENR_EN | ARMV8_PMU_USERENR_SW | \
 				 ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_ER)


ARMV8_PMU_USERENR_UEN (bit 4) was added, but ARMV8_PMU_USERENR_MASK was not updated to include it. The mask is used by KVM (and hyp switch code) to filter PMUSERENR_EL0 bits, so omitting UEN prevents guests/host-switch code from preserving or setting fine-grained per-counter EL0 access. Include ARMV8_PMU_USERENR_UEN in ARMV8_PMU_USERENR_MASK.

Copilot · 2026-04-13T03:10:01Z

+void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu)
+{
+	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
+
+	/* Hide GICv3 sysreg if necessary */
+	if (!kvm_has_gicv3(vcpu->kvm)) {
+		vgic_v3->vgic_hcr |= (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 |
+				      ICH_HCR_EL2_TC);
+		return;
+	}
+
 	if (group0_trap)
-		vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
+		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL0;
 	if (group1_trap)
-		vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
+		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TALL1;
 	if (common_trap)
-		vgic_v3->vgic_hcr |= ICH_HCR_TC;
+		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TC;
 	if (dir_trap)
-		vgic_v3->vgic_hcr |= ICH_HCR_TDIR;
+		vgic_v3->vgic_hcr |= ICH_HCR_EL2_TDIR;
 }



vcpu_set_ich_hcr() is a new non-static symbol that is called from other compilation units (e.g. kvm/sys_regs.c), but there is no visible prototype in any included header. This will trigger an implicit-function-declaration build failure under the kernel's warning settings. Add an extern declaration to an appropriate header (e.g. arch/arm64/kvm/vgic/vgic.h) and include it where needed, or make the function static and provide a properly declared helper in the right header.

[ Upstream commit 5d5b4e8 ] SVE 2.1 introduced a new feature FEAT_SVE_B16B16 which adds instructions supporting the BFloat16 floating point format. Report this to userspace through the ID registers and hwcap. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230915-arm64-zfr-b16b16-el0-v1-1-f9aba807bdb5@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 5d5b4e8) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 338a835 ] FEAT_LRCPC3 adds more instructions to support the Release Consistency model. Add a HWCAP so that userspace can make decisions about instructions it can use. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20230919162757.2707023-2-joey.gouly@arm.com [catalin.marinas@arm.com: change the HWCAP number] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 338a835) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 94d0657 ] Add HWCAP for FEAT_LSE128 (128-bit Atomic instructions). Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20231003124544.858804-2-joey.gouly@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 94d0657) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit f35c32c ] We now have *two* values for CTR_EL0.L1Ip that are reserved. Which makes things a bit awkward. In order to lift the ambiguity, rename RESERVED (0b01) to RESERVED_AIVIVT, and VPIPT (0b00) to RESERVED_VPIPT. This makes it clear which of these meant what, and I'm sure archeologists will find it useful... Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20231204143606.1806432-4-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit f35c32c) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 256f442 ] The 2023-09 release of the architecture XML (DDI0601) adds a new field ATS1E1A to HFGITR_EL2, update our definition of the register to match. This was extracted from Faud Tabba's patch "KVM: arm64: Add latest HFGITR_EL2 FGT entries to nested virt" [Extracted the sysreg definition from Faud's original patch and reword subject to match -- broonie] Signed-off-by: Fuad Tabba <tabba@google.com> Message-Id: <20231206100503.564090-4-tabba@google.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-1-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 256f442) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 41bb68f ] Add a definition of HAFGRTR_EL2 (fine grained trap control for the AMU) as per DDI0601 2023-09. This was extracted from Fuad Tabba's patch "KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt". Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231206100503.564090-6-tabba@google.com [Extract sysreg update and rewrite commit message -- broonie] Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-2-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 41bb68f) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit c0c5a8e ] Add POR_EL{0,1} according to DDI0601 2023-03. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-3-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit c0c5a8e) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 35768b2 ] Add E0POE bit that traps accesses to POR_EL0 from EL0. Updated according to DDI0601 2023-03. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-4-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 35768b2) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 9fb5dc5 ] DDI0601 2023-09 defines a new system register ID_AA64PFR2_EL1 which enumerates FPMR and some new MTE features. Add a definition of this register. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-5-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 9fb5dc5) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 6e3dcfd ] DDI0601 2023-09 defines some new fields in previously RES0 space in ID_AA64ISAR2_EL1, together with one new enum value. Update the system register definition to reflect this. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-6-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 6e3dcfd) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit b5aefb6 ] DDI0601 2023-09 adds a new system register ID_AA64ISAR3_EL1 enumerating new floating point and TLB invalidation features. Add a defintion for it. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-7-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit b5aefb6) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 9e4f409 ] DDI0601 2023-09 defines a new feature register ID_AA64FPFR0_EL1 which enumerates a number of FP8 related features. Add a definition for it. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-8-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 9e4f409) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 8afe582 ] The 2023-09 release of DDI0601 defines a number of new feature enumeration fields in ID_AA64SMFR0_EL1. Add these fields. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-9-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 8afe582) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit a605228 ] DDI0601 2023-09 defines some new fields in SCTLR_EL1 controlling new MTE and floating point features. Update our sysreg definition to reflect these. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-10-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit a605228) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 126cb3a ] DDI0601 2023-09 defines new fields in HCRX_EL2 controlling access to new system registers, update our definition of HCRX_EL2 to reflect this. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-11-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 126cb3a) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit e3a649e ] DDI0601 2023-09 defines a new sysrem register FPMR (Floating Point Mode Register) which configures the new FP8 features. Add a definition of this register. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-12-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit e3a649e) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit e94e06d ] FEAT_GCS introduces a number of new system registers. Add the registers available up to EL2 to sysreg as per DDI0601 2022-12. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20231209-b4-arm64-sysreg-additions-v1-13-45284e538474@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit e94e06d) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 3b077ad ] Add the Pauth_LR field definitions to ID_AA64ISAR1_EL1, based on DDI0601 2023-09. These fields aren't used yet. Adding them for completeness and consistency (definition already exists for ID_AA64ISAR2_EL1). Signed-off-by: Fuad Tabba <tabba@google.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231214100158.2305400-2-tabba@google.com Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 3b077ad) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 4f101cd ] Add the ExtTrcBuff field definitions to ID_AA64DFR0_EL1 from DDI0601 2023-09. This field isn't used yet. Adding it for completeness and because it will be used in future patches. Signed-off-by: Fuad Tabba <tabba@google.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231214100158.2305400-3-tabba@google.com Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 4f101cd) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 885c6d8 ] Add the definitions of missing system registers that are trappable by fine grain traps. The definitions are based on DDI0601 2023-09. Signed-off-by: Fuad Tabba <tabba@google.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20231214100158.2305400-4-tabba@google.com Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 885c6d8) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit cfc680b ] ARMv9.5 has infroduced ID_AA64MMFR4_EL1 with a bunch of new features. Add the corresponding layout. This is extracted from the public ARM SysReg_xml_A_profile-2023-09 delivery, timestamped d55f5af8e09052abe92a02adf820deea2eaed717. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Miguel Luis <miguel.luis@oracle.com> Link: https://lore.kernel.org/r/20240122181344.258974-5-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev> (cherry picked from commit cfc680b) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

(cherry picked from commit 2aea7b7)

[ Upstream commit aeddd5b ] Despite having the control bits for FEAT_SPECRES and FEAT_PACM, the ID registers fields are either incomplete or missing. Fix it. Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20240214131827.2856277-2-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev> (cherry picked from commit aeddd5b) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit fdd867f ] This adds register fields for ID_AA64DFR1_EL1 as per the definitions based on DDI0601 2023-12. Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240220023203.3091229-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit fdd867f) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 7accfaa ] This updates ID_DFR0_EL1.PerfMon and ID_DFR0_EL1.CopDbg register fields as per the definitions based on DDI0601 2023-12. Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240220025343.3093955-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 7accfaa) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 358fee2 ] This updates ID_AA64DFR0_EL1.PMSVer and ID_AA64DFR0_EL1.DebugVer register fields as per the definitions based on DDI0601 2023-12. Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240220034829.3098373-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 358fee2) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit f3dfcd2 ] Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM. Hence, correct them to reflect ARM ARM. Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20240718215532.616447-1-rananta@google.com Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit f3dfcd2) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

The PMUv3 and KVM code each have a define for the PMU cycle counter index. Move KVM's define to a shared location and use it for PMUv3 driver. Reviewed-by: Marc Zyngier <maz@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-5-280a8d7ff465@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 126d7d7)

[ Upstream commit f9b11aa ] ARMV8_PMU_COUNTER_MASK is really a mask for the PMSELR_EL0.SEL register field. Make that clear by adding a standard sysreg definition for the register, and using it instead. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-4-280a8d7ff465@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit f9b11aa) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit d8226d8 ] Armv9.4/8.9 PMU adds optional support for a fixed instruction counter similar to the fixed cycle counter. Support for the feature is indicated in the ID_AA64DFR1_EL1 register PMICNTR field. The counter is not accessible in AArch32. Existing userspace using direct counter access won't know how to handle the fixed instruction counter, so we have to avoid using the counter when user access is requested. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-7-280a8d7ff465@kernel.org Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit d8226d8) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

[ Upstream commit 0349934 ] ID_AA64MMFR1_EL1 has been updated by the architecture to enumerate several new architectural features since the last time sysreg was updated, sync with the definnition in DD0601 2024-09 to include two new versions of each of ETS and HAFDBS. Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241011-arm64-aa64mmfr1-2024-09-v1-1-61935a085010@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 0349934) Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>

Avenger-285714 · 2026-04-13T11:03:39Z

these series pr is not ready

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Avenger-285714 force-pushed the cca-prepare-001 branch 2 times, most recently from d7eab81 to 361e4a4 Compare April 13, 2026 04:17

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arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and VARange

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(cherry picked from commit 2aea7b7)

Avenger-285714 force-pushed the cca-prepare-001 branch from 361e4a4 to 64f4a4e Compare April 13, 2026 10:56

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[WIP] [linux-6.6.y] [Upstream] arm64: Backport sysreg/cpufeature/PMU infrastructure from mainline (v6.7–v6.18) for CCA prerequisite （001）#1615

[WIP] [linux-6.6.y] [Upstream] arm64: Backport sysreg/cpufeature/PMU infrastructure from mainline (v6.7–v6.18) for CCA prerequisite （001）#1615
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